This provides a macro that allows us to update all the arbitrary blit
commands we have stuck throughout the code. It assumes we don't actually
use 64b relocs (which is currently true). This also allows us to easily find
all the areas we need to update later when we really use the upper dword.
This block was done mostly with a sed job, and represents the easier
in test blit implementations.
v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
It was previously printing ironlake_debug_regs and haswell_debug_regs.
Since ironlake_debug_regs contains a lot of registers that don't exist
on Haswell, running intel_reg_dumper on Haswell caused "unclaimed
register" messages. Now I've copied the existing registers from
ironlake_debug_regs to haswell_debug_regs, so we won't print the
registers that don't exist anymore.
Also removed DP_TP_STATUS_A since it doesn't exist.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Solaris <sys/types.h> already has #define NOPID (pid_t)(-1)
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For now, only print their content for diffing, but also add the necessary
bits that can be used for more verbose output in the fugure.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
I was interested in finding why my IVB system is not getting GPU turbo
after suspend/resume. The piece that looks weird to me is that
INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's
0x12000000.
Right now, we only check for hardware DRRS support. But much more can be
done with it. Some day.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
This is something I sometimes want to do in testing, to see if a
mystery bug (say, 29172) is due to broken clock gating. Sadly, in
this case it isn't. Note that it isn't supported on non-ILK chipsets
yet.
Add four new tests for error the error handling cases:
- gem_bad_address - store to a bad address, should generate a protection or
page table error
- gem_bad_batch - try to execute a bad batch, should generate a protection,
invalid instruction or page table error
- gem_bad_blit - blit to an invalid location, should generated a protection
or page table error
- gem_hang - hang the GPU on an event that will never happen, test hang
detection & recovery code
