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intel_reg_dumper: add TRANS_VSYNCSHIFT
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3192,6 +3192,7 @@ typedef enum {
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#define TRANS_VSYNC_A 0xe0014
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#define TRANS_VSYNC_END_SHIFT 16
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#define TRANS_VSYNC_START_SHIFT 0
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#define TRANS_VSYNCSHIFT_A 0xe0028
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#define TRANSA_DATA_M1 0xe0030
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#define TRANSA_DATA_N1 0xe0034
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@ -3208,6 +3209,7 @@ typedef enum {
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#define TRANS_VTOTAL_B 0xe100c
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#define TRANS_VBLANK_B 0xe1010
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#define TRANS_VSYNC_B 0xe1014
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#define TRANS_VSYNCSHIFT_B 0xe1028
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#define TRANSB_DATA_M1 0xe1030
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#define TRANSB_DATA_N1 0xe1034
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@ -3224,6 +3226,7 @@ typedef enum {
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#define TRANS_VTOTAL_C 0xe200c
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#define TRANS_VBLANK_C 0xe2010
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#define TRANS_VSYNC_C 0xe2014
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#define TRANS_VSYNCSHIFT_C 0xe2028
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#define TRANSC_DATA_M1 0xe2030
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#define TRANSC_DATA_N1 0xe2034
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@ -1597,6 +1597,7 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
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DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
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DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
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DEFINEREG(TRANS_VSYNCSHIFT_A),
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DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
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DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
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@ -1613,6 +1614,7 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
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DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
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DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
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DEFINEREG(TRANS_VSYNCSHIFT_B),
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DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
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DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
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@ -1629,6 +1631,7 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
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DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
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DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
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DEFINEREG(TRANS_VSYNCSHIFT_C),
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DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
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DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),
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