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	reg dumper: Dump ILK panel fitting control debug registers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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				@ -3255,6 +3255,12 @@ typedef enum {
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#define PFA_CTL_1		0x68080
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#define PFB_CTL_1		0x68880
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#define  PF_ENABLE		(1<<31)
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#define PFA_CTL_2		0x68084
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#define PFB_CTL_2		0x68884
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#define PFA_CTL_3		0x68088
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#define PFB_CTL_3		0x68888
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#define PFA_CTL_4		0x68090
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#define PFB_CTL_4		0x68890
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#define PFA_WIN_POS		0x68070
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#define PFB_WIN_POS		0x68870
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@ -1284,6 +1284,27 @@ DEBUGSTRING(ironlake_debug_panel_fitting)
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		 val & (1 << 20) ? "field 0" : "field 1");
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}
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DEBUGSTRING(ironlake_debug_panel_fitting_2)
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{
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	asprintf(result,
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		 "vscale %f",
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		 val / (float) (1<<15));
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}
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DEBUGSTRING(ironlake_debug_panel_fitting_3)
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{
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	asprintf(result,
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		 "vscale initial phase %f",
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		 val / (float) (1<<15));
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}
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DEBUGSTRING(ironlake_debug_panel_fitting_4)
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{
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	asprintf(result,
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		 "hscale %f",
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		 val / (float) (1<<15));
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}
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DEBUGSTRING(ironlake_debug_pf_win)
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{
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	int a, b;
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@ -1518,10 +1539,16 @@ static struct reg_debug ironlake_debug_regs[] = {
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	DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
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	DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
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	DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
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	DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
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	DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
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	DEFINEREG2(PFA_CTL_4, ironlake_debug_panel_fitting_4),
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	DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
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	DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
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	DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
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	DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
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	DEFINEREG2(PFB_CTL_2, ironlake_debug_panel_fitting_2),
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	DEFINEREG2(PFB_CTL_3, ironlake_debug_panel_fitting_3),
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	DEFINEREG2(PFB_CTL_4, ironlake_debug_panel_fitting_4),
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	DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
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	DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
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	/* PCH */
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