flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-09 17:06:14 +00:00
Code Issues Releases Wiki Activity

Add Ironlake INSTDONE bits.

Browse Source
This commit is contained in:
Eric Anholt 2010-03-24 11:40:07 -07:00
parent 7c9d69de57
commit b0ddd0688c
3 changed files with 67 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/instdone.c
View File

@ -141,6 +141,38 @@ init_instdone_definitions(void)
gen6_instdone2_bit(GEN6_GS_DONE, "GS");
gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
gen6_instdone2_bit(GEN6_VF_DONE, "VF");
} else if (IS_IRONLAKE(devid)) {
gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");
gen4_instdone_bit(ILK_ROW_0_EU_3_DONE, "Row 0, EU 3");
gen4_instdone_bit(ILK_ROW_1_EU_0_DONE, "Row 1, EU 0");
gen4_instdone_bit(ILK_ROW_1_EU_1_DONE, "Row 1, EU 1");
gen4_instdone_bit(ILK_ROW_1_EU_2_DONE, "Row 1, EU 2");
gen4_instdone_bit(ILK_ROW_1_EU_3_DONE, "Row 1, EU 3");
gen4_instdone_bit(ILK_ROW_2_EU_0_DONE, "Row 2, EU 0");
gen4_instdone_bit(ILK_ROW_2_EU_1_DONE, "Row 2, EU 1");
gen4_instdone_bit(ILK_ROW_2_EU_2_DONE, "Row 2, EU 2");
gen4_instdone_bit(ILK_ROW_2_EU_3_DONE, "Row 2, EU 3");
gen4_instdone_bit(ILK_VCP_DONE, "VCP");
gen4_instdone_bit(ILK_ROW_0_MATH_DONE, "Row 0 math");
gen4_instdone_bit(ILK_ROW_1_MATH_DONE, "Row 1 math");
gen4_instdone_bit(ILK_ROW_2_MATH_DONE, "Row 2 math");
gen4_instdone_bit(ILK_VC1_DONE, "VC1");
gen4_instdone_bit(ILK_ROW_0_MA_DONE, "Row 0 MA");
gen4_instdone_bit(ILK_ROW_1_MA_DONE, "Row 1 MA");
gen4_instdone_bit(ILK_ROW_2_MA_DONE, "Row 2 MA");
gen4_instdone_bit(ILK_ROW_0_ISC_DONE, "Row 0 ISC");
gen4_instdone_bit(ILK_ROW_1_ISC_DONE, "Row 1 ISC");
gen4_instdone_bit(ILK_ROW_2_ISC_DONE, "Row 2 ISC");
gen4_instdone_bit(ILK_VFE_DONE, "VFE");
gen4_instdone_bit(ILK_TD_DONE, "TD");
gen4_instdone_bit(ILK_SVTS_DONE, "SVTS");
gen4_instdone_bit(ILK_TS_DONE, "TS");
gen4_instdone_bit(ILK_GW_DONE, "GW");
gen4_instdone_bit(ILK_AI_DONE, "AI");
gen4_instdone_bit(ILK_AC_DONE, "AC");
gen4_instdone_bit(ILK_AM_DONE, "AM");
} else if (IS_965(devid)) {
gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1");

32
lib/intel_reg.h
View File

@ -463,6 +463,38 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define I965_CP_DONE (1 << 1)
# define I965_RING_0_ENABLE (1 << 0)
# define ILK_ROW_0_EU_0_DONE (1 << 31)
# define ILK_ROW_0_EU_1_DONE (1 << 30)
# define ILK_ROW_0_EU_2_DONE (1 << 29)
# define ILK_ROW_0_EU_3_DONE (1 << 28)
# define ILK_ROW_1_EU_0_DONE (1 << 27)
# define ILK_ROW_1_EU_1_DONE (1 << 26)
# define ILK_ROW_1_EU_2_DONE (1 << 25)
# define ILK_ROW_1_EU_3_DONE (1 << 24)
# define ILK_ROW_2_EU_0_DONE (1 << 23)
# define ILK_ROW_2_EU_1_DONE (1 << 22)
# define ILK_ROW_2_EU_2_DONE (1 << 21)
# define ILK_ROW_2_EU_3_DONE (1 << 20)
# define ILK_VCP_DONE (1 << 19)
# define ILK_ROW_0_MATH_DONE (1 << 18)
# define ILK_ROW_1_MATH_DONE (1 << 17)
# define ILK_ROW_2_MATH_DONE (1 << 16)
# define ILK_VC1_DONE (1 << 15)
# define ILK_ROW_0_MA_DONE (1 << 14)
# define ILK_ROW_1_MA_DONE (1 << 13)
# define ILK_ROW_2_MA_DONE (1 << 12)
# define ILK_ROW_0_ISC_DONE (1 << 11)
# define ILK_ROW_1_ISC_DONE (1 << 10)
# define ILK_ROW_2_ISC_DONE (1 << 9)
# define ILK_VFE_DONE (1 << 8)
# define ILK_TD_DONE (1 << 7)
# define ILK_SVTS_DONE (1 << 6)
# define ILK_TS_DONE (1 << 5)
# define ILK_GW_DONE (1 << 4)
# define ILK_AI_DONE (1 << 3)
# define ILK_AC_DONE (1 << 2)
# define ILK_AM_DONE (1 << 1)
#define GEN6_INSTDONE_1 0x206c
# define GEN6_MA_3_DONE (1 << 31)
# define GEN6_EU_32_DONE (1 << 30)

3
tools/intel_reg_dumper.c
View File

@ -1242,6 +1242,9 @@ DEBUGSTRING(ironlake_debug_pf_win)
}
static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(GEN6_INSTDONE_1),
DEFINEREG(GEN6_INSTDONE_2),
DEFINEREG2(CPU_VGACNTRL, i830_debug_vgacntrl),
DEFINEREG(DIGITAL_PORT_HOTPLUG_CNTRL),