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https://github.com/tiagovignatti/intel-gpu-tools.git
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tools/reg_dumper: really dump pipe C regs
Not just a copy of pipe B. Meh. Also kill a few redudant #define for pipe B - they match pipe A.
This commit is contained in:
Daniel Vetter
parent
9fcaffda88
commit
0efa6c7b27
@ -1096,6 +1096,16 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define BCLRPAT_B 0x61020
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#define VSYNCSHIFT_B 0x61028
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#define HTOTAL_C 0x62000
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#define HBLANK_C 0x62004
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#define HSYNC_C 0x62008
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#define VTOTAL_C 0x6200c
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#define VBLANK_C 0x62010
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#define VSYNC_C 0x62014
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#define PIPECSRC 0x6201c
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#define BCLRPAT_C 0x62020
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#define VSYNCSHIFT_C 0x62028
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#define PP_STATUS 0x61200
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# define PP_ON (1 << 31)
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/**
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@ -2500,13 +2510,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define PIPEB_DSL 0x71000
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#define PIPEBCONF 0x71008
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#define PIPEBCONF_ENABLE (1<<31)
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#define PIPEBCONF_DISABLE 0
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#define PIPEBCONF_DOUBLE_WIDE (1<<30)
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#define PIPEBCONF_DISABLE 0
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#define PIPEBCONF_GAMMA (1<<24)
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#define PIPEBCONF_PALETTE 0
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#define PIPEBCONF 0x71008
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#define PIPEBGCMAXRED 0x71010
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#define PIPEBGCMAXGREEN 0x71014
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@ -2520,8 +2524,23 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define PIPEB_DP_LINK_M 0x71060
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#define PIPEB_DP_LINK_N 0x71064
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#define PIPECCONF 0x72008
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#define PIPECGCMAXRED 0x72010
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#define PIPECGCMAXGREEN 0x72014
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#define PIPECGCMAXBLUE 0x72018
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#define PIPECSTAT 0x72024
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#define PIPECFRAMEHIGH 0x72040
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#define PIPECFRAMEPIXEL 0x72044
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#define PIPEC_GMCH_DATA_M 0x72050
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#define PIPEC_GMCH_DATA_N 0x72054
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#define PIPEC_DP_LINK_M 0x72060
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#define PIPEC_DP_LINK_N 0x72064
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#define DSPACNTR 0x70180
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#define DSPBCNTR 0x71180
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#define DSPCCNTR 0x72180
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#define DISPLAY_PLANE_ENABLE (1<<31)
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#define DISPLAY_PLANE_DISABLE 0
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#define DISPLAY_PLANE_TILED (1<<10)
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@ -2557,6 +2576,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define DSPBADDR DSPBBASE
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#define DSPBSTRIDE 0x71188
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#define DSPCBASE 0x72184
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#define DSPCADDR DSPCBASE
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#define DSPCSTRIDE 0x72188
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#define DSPAKEYVAL 0x70194
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#define DSPAKEYMASK 0x70198
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@ -2571,6 +2594,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define DSPBSURF 0x7119C
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#define DSPBTILEOFF 0x711A4
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#define DSPCSURF 0x7219C
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#define DSPCTILEOFF 0x721A4
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#define VGACNTRL 0x71400
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# define VGA_DISP_DISABLE (1 << 31)
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# define VGA_2X_MODE (1 << 30)
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@ -2977,24 +3003,30 @@ typedef enum {
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/* PIPEB timing regs are same start from 0x61000 */
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#define PIPEB_DATA_M1 0x61030
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#define PIPEB_DATA_M1_OFFSET 0
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#define PIPEB_DATA_N1 0x61034
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#define PIPEB_DATA_N1_OFFSET 0
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#define PIPEB_DATA_M2 0x61038
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#define PIPEB_DATA_M2_OFFSET 0
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#define PIPEB_DATA_N2 0x6103c
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#define PIPEB_DATA_N2_OFFSET 0
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#define PIPEB_LINK_M1 0x61040
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#define PIPEB_LINK_M1_OFFSET 0
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#define PIPEB_LINK_N1 0x61044
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#define PIPEB_LINK_N1_OFFSET 0
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#define PIPEB_LINK_M2 0x61048
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#define PIPEB_LINK_M2_OFFSET 0
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#define PIPEB_LINK_N2 0x6104c
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#define PIPEB_LINK_N2_OFFSET 0
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/* PIPEC timing regs */
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#define PIPEC_DATA_M1 0x62030
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#define PIPEC_DATA_N1 0x62034
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#define PIPEC_DATA_M2 0x62038
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#define PIPEC_DATA_N2 0x6203c
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#define PIPEC_LINK_M1 0x62040
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#define PIPEC_LINK_N1 0x62044
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#define PIPEC_LINK_M2 0x62048
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#define PIPEC_LINK_N2 0x6204c
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/* PIPECONF for pipe A/B addr is same */
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@ -1646,6 +1646,37 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG(DSPBSURF),
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DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
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/* pipe C */
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DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
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DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
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DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
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DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
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DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
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DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
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DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
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DEFINEREG(VSYNCSHIFT_C),
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DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
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DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
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DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
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DEFINEREG2(PIPEC_DATA_M2, ironlake_debug_m_tu),
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DEFINEREG2(PIPEC_DATA_N2, ironlake_debug_n),
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DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
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DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
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DEFINEREG2(PIPEC_LINK_M2, ironlake_debug_n),
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DEFINEREG2(PIPEC_LINK_N2, ironlake_debug_n),
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DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
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DEFINEREG(DSPCBASE),
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DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
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DEFINEREG(DSPCSURF),
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DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
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/* Panel fitter */
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DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
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DEFINEREG2(PFA_CTL_2, ironlake_debug_panel_fitting_2),
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DEFINEREG2(PFA_CTL_3, ironlake_debug_panel_fitting_3),
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@ -1665,35 +1696,6 @@ static struct reg_debug ironlake_debug_regs[] = {
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DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
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DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
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/* pipe C */
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DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
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DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
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DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
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DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
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DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
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DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
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DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
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DEFINEREG(VSYNCSHIFT_B),
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DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
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DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
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DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
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DEFINEREG2(PIPEB_DATA_M2, ironlake_debug_m_tu),
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DEFINEREG2(PIPEB_DATA_N2, ironlake_debug_n),
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DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
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DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
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DEFINEREG2(PIPEB_LINK_M2, ironlake_debug_n),
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DEFINEREG2(PIPEB_LINK_N2, ironlake_debug_n),
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DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
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DEFINEREG(DSPBBASE),
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DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
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DEFINEREG(DSPBSURF),
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DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
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/* PCH */
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DEFINEREG2(PCH_DREF_CONTROL, ironlake_debug_dref_ctl),
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