2dac0a19a4
Add support for destination writemasks.
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This involved changing dest operands to have their own structure like src
operands, as the destination writemask (which is align16-only) shares space
with register numbers in align1 mode.
2013-03-04 15:54:23 +00:00
de1a889fe3
Avoid shift/reduce conflict in predicate by making flagreg and subreg 1 token.
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Thanks to keithp for pointing out where the conflict was.
2013-03-04 15:54:23 +00:00
0ed5d93cc2
Add support for predicate control.
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This is untested on programs using predicate control, and also causes a
shift/reduce conflict.
2013-03-04 15:54:22 +00:00
6a88ada7e8
Add support for swizzle control on source operands.
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This required restructuring to store source operands in a new structure rather
than being stored in instructions, as swizzle is align16-only and shares
storage with other fields for align1 mode.
These changes were not tested on real programs using swizzle.
2013-03-04 15:54:22 +00:00
2a0f135784
Add acc[01] as src operands.
2013-03-04 15:54:22 +00:00
edc82a045c
Comment cleanup and add missing semicolons after rules.
2013-03-04 15:54:22 +00:00
908f37d92d
Add support for more instruction options.
2013-03-04 15:54:22 +00:00
6db54d7465
Typo fix in comment.
2013-03-04 15:54:22 +00:00
1d7d04228e
Rename direct_gen_reg struct to direct_reg now that it fills more roles.
2013-03-04 15:54:22 +00:00
5297b2a7e8
Support src ARF operands in another place, and spell it arch instead of acc.
2013-03-04 15:54:22 +00:00
2c7876583e
Add support for more registers as source operands.
2013-03-04 15:54:22 +00:00
883408eab8
Add rules for more registers, and use some for destinations.
2013-03-04 15:54:22 +00:00
2cca382cd2
Rename the resulting binary to gen4asm instead of lextest.
2013-03-04 15:54:22 +00:00
c81a6084de
Add a negation that the initial disasm missed.
2013-03-04 15:54:22 +00:00
f914c6ace2
Add many more opcodes.
2013-03-04 15:54:22 +00:00
569990bf6b
Lex the register number with the register name.
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This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW
being lexed as GENREG NUMBER LANGLE etc. rather than
GENREG INTEGER DOT INTEGER LANGLE etc.
2013-03-04 15:54:22 +00:00
3d36079ae3
Add syntax for extended math send functions, and adjust packed_yuv_sf for it.
2013-03-04 15:54:22 +00:00
e865196a9d
Add a syntax for urb write messages.
2013-03-04 15:54:21 +00:00
5232981c88
Add some more generated files to ignore.
2013-03-04 15:54:21 +00:00
bf0b5ddbe7
Add packed yuv sf kernel from 2d driver.
2013-03-04 15:54:21 +00:00
43313946e7
Add syntax for translating the DP write send message.
2013-03-04 15:54:21 +00:00
16324215b2
Fix respecting of instruction options (misunderstood default action behavior).
2013-03-04 15:54:21 +00:00
56c4ccfc19
Fix up sampler send message translation and give it a near-usable syntax.
2013-03-04 15:54:21 +00:00
e609d6ba93
Zero out the initial header instoptions.
2013-03-04 15:54:21 +00:00
2093218bcd
There's no reason to provide typing or region on the null register.
2013-03-04 15:54:21 +00:00
56b50b6803
bzero instructions before filling in the bits we care about.
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This avoids some set bits in padding fields.
2013-03-04 15:54:21 +00:00
7c330fbf3a
Fill in type of null register to match Mesa.
2013-03-04 15:54:21 +00:00
ac32bb09eb
This code was supposed to be null instead of acc0 (brw_disasm.c gave "a0").
2013-03-04 15:54:21 +00:00
a34d1e0d8c
Fix translation of message registers.
2013-03-04 15:54:21 +00:00
90aea51983
Fix translation of saturate value, and wire conditionalmod to 0 for now.
2013-03-04 15:54:21 +00:00
b9e6224587
Remove generated source from repo.
2013-03-04 15:54:21 +00:00
dc96c56d9e
Add support for negate and abs to source operands.
2013-03-04 15:54:21 +00:00
0d929b430b
Fix imm32 translation.
2013-03-04 15:54:20 +00:00
0edcb2561d
Fix dest_horiz_stride translation, and destination type.
2013-03-04 15:54:20 +00:00
b798c7c9da
And add a comma. This was supposed to be a minor change.
2013-03-04 15:54:20 +00:00
fc022c1bc2
Remove generated file.
2013-03-04 15:54:20 +00:00
d4c82e8278
Fix horizontal stride translation.
2013-03-04 15:54:20 +00:00
f2f18561e5
C warnings cleanup.
2013-03-04 15:54:20 +00:00
1c62350848
Add Wall.
2013-03-04 15:54:20 +00:00
a58d896dfe
actually print out last uint32_t of instruction.
2013-03-04 15:54:20 +00:00
19f1c1cec4
Start correcting the translation.
2013-03-04 15:54:20 +00:00
6c98c8d578
Get the wm program to parse.
2013-03-04 15:54:20 +00:00
22a1063cc0
Initial gen4asm code.
2013-03-04 15:54:20 +00:00
7ee278f176
build: Guard the inclusions of config.h with HAVE_CONFIG_H
...
autoconf can be configured to not generate a config.h but to give the
defines with command line arguments instead. In this case, there's no
config.h to include.
To work in both cases autoconf adds a HAVE_CONFIG_H define on the command
line to signal there's a config.h to include.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com >
2013-03-04 15:45:34 +00:00
aa2bd8a692
lib: Allow to override the device id at run time
...
Using the same environment variable as libdrm so one doesn't have to
remember two different things. This is helpful to run a test under a
fake identity, to, say, dump an aub file.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com >
2013-03-04 15:45:18 +00:00
75f52a6e3b
lib: Factor out a function to check if an environment variable is set
...
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com >
2013-03-04 15:45:18 +00:00
6c04309579
intel_chipset: Fix Haswell CRW PCI IDs.
...
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2013-03-03 19:54:32 +01:00
2155b16af2
quick_dump: prettier printing
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net >
2013-02-21 18:31:20 -08:00
cf17d10828
fix arch build: update ax_python_devel.m4
...
I complained about the broken m4 script, and it got fixed. I love the
internet.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net >
2013-02-19 10:29:13 -08:00
84b525cf46
intel_chipset: Add multiple inclusion guards into intel_chipset.h
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch >
2013-02-19 13:55:08 +01:00
Eric Anholt