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https://github.com/tiagovignatti/intel-gpu-tools.git
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Fix imm32 translation.
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0edcb2561d
commit
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@ -80,7 +80,7 @@
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> specialinstruction
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm
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%type <instruction> directsrcaccoperand src directsrcoperand srcimm imm32reg
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%type <instruction> srcacc srcaccimm
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%type <instruction> instoptions instoption_list
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%type <program> instrseq
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@ -270,32 +270,19 @@ dstreg: directgenreg
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;
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/* 1.4.3: Source register */
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srcaccimm: srcacc
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| imm32 srcimmtype
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{
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$$.bits1.da1.src0_reg_file = BRW_IMMEDIATE_VALUE;
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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$$.bits3.ud = $1;
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break;
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case BRW_REGISTER_TYPE_D:
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$$.bits3.id = $1;
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break;
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case BRW_REGISTER_TYPE_F:
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$$.bits3.fd = $1;
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break;
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}
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}
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srcaccimm: srcacc | imm32reg
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;
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/* XXX: indirectsrcaccoperand */
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srcacc: directsrcaccoperand
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;
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srcimm: directsrcoperand
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| imm32 srcimmtype
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srcimm: directsrcoperand | imm32reg
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imm32reg: imm32 srcimmtype
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{
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$$.bits1.da1.src0_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src0_reg_type = $2;
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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$$.bits3.ud = $1;
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@ -303,9 +290,28 @@ srcimm: directsrcoperand
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case BRW_REGISTER_TYPE_D:
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$$.bits3.id = $1;
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break;
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case BRW_REGISTER_TYPE_UW:
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$$.bits3.ud = $1;
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break;
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case BRW_REGISTER_TYPE_W:
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$$.bits3.id = $1;
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break;
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case BRW_REGISTER_TYPE_UB:
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$$.bits3.ud = $1;
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/* There is no native byte immediate type */
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$$.bits1.da1.src0_reg_type = BRW_REGISTER_TYPE_UD;
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break;
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case BRW_REGISTER_TYPE_B:
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$$.bits3.id = $1;
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/* There is no native byte immediate type */
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$$.bits1.da1.src0_reg_type = BRW_REGISTER_TYPE_D;
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break;
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case BRW_REGISTER_TYPE_F:
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$$.bits3.fd = $1;
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break;
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default:
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fprintf(stderr, "unknown immediate type %d\n", $2);
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YYERROR;
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}
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}
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;
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@ -427,7 +433,7 @@ regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
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| TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; }
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| TYPE_D { $$ = BRW_REGISTER_TYPE_D; }
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| TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; }
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| TYPE_W { $$ = BRW_REGISTER_TYPE_UW; }
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| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
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| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
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| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
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/* XXX: Add TYPE_VF and TYPE_HF */
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