mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 17:36:11 +00:00
Add support for destination writemasks.
This involved changing dest operands to have their own structure like src operands, as the destination writemask (which is align16-only) shares space with register numbers in align1 mode.
This commit is contained in:
Eric Anholt
Damien Lespiau
parent
de1a889fe3
commit
2dac0a19a4
@ -38,6 +38,21 @@ typedef float GLfloat;
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void yyerror (char *msg);
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/**
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* This structure is the internal representation of destination operands in the
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* parser.
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*/
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struct dst_operand {
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int reg_file, reg_nr, subreg_nr, reg_type;
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int writemask_set;
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int writemask;
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int horiz_stride;
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int address_mode; /* 0 if direct, 1 if register-indirect */
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int indirect_offset;
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};
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/**
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* This structure is the internal representation of source operands in the
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* parser.
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154
assembler/gram.y
154
assembler/gram.y
@ -49,6 +49,7 @@
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} direct_reg;
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double imm32;
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struct dst_operand dst_operand;
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struct src_operand src_operand;
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}
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@ -82,7 +83,7 @@
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%token MSGLEN RETURNLEN
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%token <integer> ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE
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%token SATURATE
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%token SATURATE X Y Z W
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%token <integer> INTEGER
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%token <number> NUMBER
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@ -96,13 +97,13 @@
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%type <instruction> instruction unaryinstruction binaryinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> specialinstruction
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> post_dst msgtarget
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%type <instruction> msgtarget
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%type <instruction> instoptions instoption_list predicate
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%type <program> instrseq
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%type <integer> instoption
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%type <integer> unaryop binaryop binaryaccop
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%type <integer> conditionalmodifier saturate negate abs chansel
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%type <integer> writemask_x writemask_y writemask_z writemask_w
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> subregnum sampler_datatype
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%type <integer> urb_swizzle urb_allocate urb_used urb_complete
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@ -115,6 +116,7 @@
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%type <direct_reg> dstoperandex_typed srcarchoperandex_typed
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%type <integer> mask_subreg maskstack_subreg maskstackdepth_subreg
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%type <imm32> imm32
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%type <dst_operand> dst dstoperand dstoperandex dstreg post_dst writemask
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%type <src_operand> directsrcoperand srcarchoperandex directsrcaccoperand
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%type <src_operand> src srcimm imm32reg payload srcacc srcaccimm swizzle
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%%
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@ -171,7 +173,8 @@ unaryinstruction:
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$$.header.execution_size = $5;
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set_instruction_options(&$$, &$8);
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set_instruction_predicate(&$$, &$1);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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}
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@ -191,7 +194,8 @@ binaryinstruction:
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$$.header.execution_size = $5;
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set_instruction_options(&$$, &$9);
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set_instruction_predicate(&$$, &$1);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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@ -213,7 +217,8 @@ binaryaccinstruction:
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$$.header.execution_size = $5;
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set_instruction_options(&$$, &$9);
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set_instruction_predicate(&$$, &$1);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_dest(&$$, &$6) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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@ -244,7 +249,8 @@ sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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$$.header.execution_size = $3;
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$$.header.destreg__conditionalmod = $4; /* msg reg index */
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set_instruction_predicate(&$$, &$1);
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set_instruction_dest(&$$, &$5);
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if (set_instruction_dest(&$$, &$5) != 0)
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YYERROR;
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if (set_instruction_src0(&$$, &$6) != 0)
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YYERROR;
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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@ -399,15 +405,18 @@ math_scalar: /* empty */ { $$ = 0; }
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dst: dstoperand | dstoperandex
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;
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/* XXX: writemask */
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dstoperand: dstreg dstregion regtype
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dstoperand: dstreg dstregion writemask regtype
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{
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/* Returns an instruction with just the destination register
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* filled in.
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*/
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$$.bits1 = $1.bits1;
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$$.bits1.da1.dest_horiz_stride = $2;
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$$.bits1.da1.dest_reg_type = $3;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = $2;
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$$.writemask_set = $3.writemask_set;
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$$.writemask = $3.writemask;
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$$.reg_type = $4;
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}
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;
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@ -416,43 +425,43 @@ dstoperand: dstreg dstregion regtype
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*/
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dstoperandex: dstoperandex_typed dstregion regtype
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.bits1.da1.dest_horiz_stride = $2;
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$$.bits1.da1.dest_reg_type = $3;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = $2;
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$$.reg_type = $3;
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}
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| maskstackreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.bits1.da1.dest_horiz_stride = 1;
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$$.bits1.da1.dest_reg_type = BRW_REGISTER_TYPE_UW;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = 1;
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$$.reg_type = BRW_REGISTER_TYPE_UW;
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}
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| controlreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.bits1.da1.dest_horiz_stride = 1;
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$$.bits1.da1.dest_reg_type = BRW_REGISTER_TYPE_UD;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = 1;
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$$.reg_type = BRW_REGISTER_TYPE_UD;
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}
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| ipreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.bits1.da1.dest_horiz_stride = 1;
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$$.bits1.da1.dest_reg_type = BRW_REGISTER_TYPE_UD;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = 1;
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$$.reg_type = BRW_REGISTER_TYPE_UD;
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}
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| nullreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.bits1.da1.dest_horiz_stride = 1;
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$$.bits1.da1.dest_reg_type = BRW_REGISTER_TYPE_F;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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$$.horiz_stride = 1;
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$$.reg_type = BRW_REGISTER_TYPE_F;
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}
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;
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@ -462,15 +471,15 @@ dstoperandex_typed: accreg | flagreg | addrreg | maskreg
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/* XXX: indirectgenreg, indirectmsgreg */
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dstreg: directgenreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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}
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| directmsgreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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$$.bits1.da1.dest_reg_nr = $1.reg_nr;
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$$.bits1.da1.dest_subreg_nr = $1.subreg_nr;
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$$.reg_file = $1.reg_file;
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$$.reg_nr = $1.reg_nr;
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$$.subreg_nr = $1.subreg_nr;
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}
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;
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@ -863,6 +872,33 @@ swizzle: /* empty */
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chansel: X | Y | Z | W
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;
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/* 1.4.9: Write mask */
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/* Returns a partially completed dst_operand, with just the writemask bits
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* filled out.
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*/
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writemask: /* empty */
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{
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$$.writemask_set = 0;
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$$.writemask = 0xf;
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}
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| DOT writemask_x writemask_y writemask_z writemask_w
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{
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$$.writemask_set = 1;
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$$.writemask = $2 | $3 | $4 | $5;
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}
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writemask_x: /* empty */ { $$ = 0; }
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| X { $$ = 1 << BRW_CHANNEL_X; }
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writemask_y: /* empty */ { $$ = 0; }
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| Y { $$ = 1 << BRW_CHANNEL_Y; }
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writemask_z: /* empty */ { $$ = 0; }
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| Z { $$ = 1 << BRW_CHANNEL_Z; }
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writemask_w: /* empty */ { $$ = 0; }
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| W { $$ = 1 << BRW_CHANNEL_W; }
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/* 1.4.11: Immediate values */
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imm32: INTEGER { $$ = $1; }
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| NUMBER { $$ = $1; }
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@ -1013,15 +1049,31 @@ void yyerror (char *msg)
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/**
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* Fills in the destination register information in instr from the bits in dst.
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*/
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void set_instruction_dest(struct brw_instruction *instr,
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struct brw_instruction *dest)
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int set_instruction_dest(struct brw_instruction *instr,
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struct dst_operand *dest)
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{
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instr->bits1.da1.dest_reg_file = dest->bits1.da1.dest_reg_file;
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instr->bits1.da1.dest_reg_type = dest->bits1.da1.dest_reg_type;
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instr->bits1.da1.dest_subreg_nr = dest->bits1.da1.dest_subreg_nr;
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instr->bits1.da1.dest_reg_nr = dest->bits1.da1.dest_reg_nr;
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instr->bits1.da1.dest_horiz_stride = dest->bits1.da1.dest_horiz_stride;
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instr->bits1.da1.dest_address_mode = dest->bits1.da1.dest_address_mode;
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if (instr->header.access_mode == BRW_ALIGN_1) {
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instr->bits1.da1.dest_reg_file = dest->reg_file;
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instr->bits1.da1.dest_reg_type = dest->reg_type;
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instr->bits1.da1.dest_subreg_nr = dest->subreg_nr;
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instr->bits1.da1.dest_reg_nr = dest->reg_nr;
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instr->bits1.da1.dest_horiz_stride = dest->horiz_stride;
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instr->bits1.da1.dest_address_mode = dest->address_mode;
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if (dest->writemask_set) {
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fprintf(stderr, "error: write mask set in align1 "
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"instruction\n");
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return 1;
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}
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} else {
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instr->bits1.da16.dest_reg_file = dest->reg_file;
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instr->bits1.da16.dest_reg_type = dest->reg_type;
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instr->bits1.da16.dest_subreg_nr = dest->subreg_nr;
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instr->bits1.da16.dest_reg_nr = dest->reg_nr;
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instr->bits1.da16.dest_address_mode = dest->address_mode;
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instr->bits1.da16.dest_writemask = dest->writemask;
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}
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return 0;
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}
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/* Sets the first source operand for the instruction. Returns 0 on success. */
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