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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 17:36:11 +00:00
Comment cleanup and add missing semicolons after rules.
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@ -190,6 +190,7 @@ binaryinstruction:
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;
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binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2
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;
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binaryaccinstruction:
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predicate binaryaccop conditionalmodifier saturate execsize
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@ -211,6 +212,7 @@ binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN
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;
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triinstruction: sendinstruction
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;
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sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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@ -238,11 +240,13 @@ sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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$$.bits3.generic.end_of_thread =
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$12.bits3.generic.end_of_thread;
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}
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;
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branchloopop: IF | IFF | WHILE
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;
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breakop: BREAK | CONT | WAIT
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;
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maskpushop: MSAVE | PUSH
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;
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@ -252,6 +256,7 @@ specialinstruction: NOP
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bzero(&$$, sizeof($$));
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$$.header.opcode = $1;
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}
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;
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/* XXX! */
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payload: directsrcoperand
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@ -368,16 +373,18 @@ math_function: INV | LOG | EXP | SQRT | POW | SIN | COS | SINCOS | INTDIV
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math_signed: /* empty */ { $$ = 0; }
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| SIGNED { $$ = 1; }
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;
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math_scalar: /* empty */ { $$ = 0; }
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| SCALAR { $$ = 1; }
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;
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/* 1.4.2: Destination register */
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dst: dstoperand | dstoperandex
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;
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/* XXX: dstregion writemask */
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/* XXX: writemask */
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dstoperand: dstreg dstregion regtype
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{
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/* Returns an instruction with just the destination register
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@ -437,7 +444,7 @@ dstoperandex: dstoperandex_typed dstregion regtype
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dstoperandex_typed: accreg | flagreg | addrreg | maskreg
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;
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/* XXX: indirectgenreg, directmsgreg, indirectmsgreg */
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/* XXX: indirectgenreg, indirectmsgreg */
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dstreg: directgenreg
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{
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$$.bits1.da1.dest_reg_file = $1.reg_file;
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@ -461,6 +468,7 @@ srcacc: directsrcaccoperand
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;
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srcimm: directsrcoperand | imm32reg
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;
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imm32reg: imm32 srcimmtype
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{
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@ -568,6 +576,7 @@ directsrcoperand:
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| srcarchoperandex
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;
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/* 1.4.5: Register files and register numbers */
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subregnum: DOT INTEGER
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{
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$$ = $2;
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@ -579,13 +588,13 @@ subregnum: DOT INTEGER
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}
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;
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/* 1.4.5: Register files and register numbers */
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directgenreg: GENREG subregnum
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{
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$$.reg_file = BRW_GENERAL_REGISTER_FILE;
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$$.reg_nr = $1;
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$$.subreg_nr = $2;
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}
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;
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directmsgreg: MSGREG subregnum
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{
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@ -794,13 +803,16 @@ regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
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| TYPE_W { $$ = BRW_REGISTER_TYPE_W; }
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| TYPE_UB { $$ = BRW_REGISTER_TYPE_UB; }
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| TYPE_B { $$ = BRW_REGISTER_TYPE_B; }
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;
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/* XXX: Add TYPE_VF and TYPE_HF */
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srcimmtype: regtype
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;
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/* 1.4.11: */
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/* 1.4.11: Immediate values */
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imm32: INTEGER { $$ = $1; }
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| NUMBER { $$ = $1; }
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;
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/* 1.4.12: Predication and modifiers */
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/* XXX: do the predicate */
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@ -809,9 +821,11 @@ predicate:
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negate: /* empty */ { $$ = 0; }
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| MINUS { $$ = 1; }
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;
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abs: /* empty */ { $$ = 0; }
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| ABS { $$ = 1; }
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;
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execsize: LPAREN INTEGER RPAREN
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{
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