mirror of
https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-20 22:36:24 +00:00
Add support for swizzle control on source operands.
This required restructuring to store source operands in a new structure rather than being stored in instructions, as swizzle is align16-only and shares storage with other fields for align1 mode. These changes were not tested on real programs using swizzle.
This commit is contained in:
Eric Anholt
Damien Lespiau
parent
2a0f135784
commit
6a88ada7e8
@ -26,6 +26,8 @@
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*
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*/
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#include <sys/types.h>
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typedef unsigned char GLubyte;
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typedef short GLshort;
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typedef unsigned int GLuint;
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@ -36,6 +38,26 @@ typedef float GLfloat;
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void yyerror (char *msg);
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/**
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* This structure is the internal representation of source operands in the
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* parser.
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*/
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struct src_operand {
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int reg_file, reg_nr, subreg_nr, reg_type;
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int abs, negate;
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int horiz_stride, width, vert_stride;
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int address_mode; /* 0 if direct, 1 if register-indirect */
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int indirect_offset; /* XXX */
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int swizzle_set;
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int swizzle_x, swizzle_y, swizzle_z, swizzle_w;
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uint32_t imm32; /* only set if reg_file == BRW_IMMEDIATE_VALUE */
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} src_operand;
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/**
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* This structure is just the list container for instructions accumulated by
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* the parser.
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274
assembler/gram.y
274
assembler/gram.y
@ -48,6 +48,8 @@
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int reg_file, reg_nr, subreg_nr;
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} direct_reg;
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double imm32;
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struct src_operand src_operand;
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}
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%token SEMICOLON
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@ -88,18 +90,18 @@
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%token <integer> INTDIVMOD
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%token SIGNED SCALAR
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%token <integer> X Y Z W
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%type <instruction> instruction unaryinstruction binaryinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> specialinstruction
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%type <instruction> dst dstoperand dstoperandex dstreg
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%type <instruction> directsrcaccoperand srcarchoperandex src directsrcoperand
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%type <instruction> srcimm imm32reg
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%type <instruction> srcacc srcaccimm payload post_dst msgtarget
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%type <instruction> post_dst msgtarget
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%type <instruction> instoptions instoption_list
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%type <program> instrseq
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%type <integer> instoption
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%type <integer> unaryop binaryop binaryaccop
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%type <integer> conditionalmodifier saturate negate abs
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%type <integer> conditionalmodifier saturate negate abs chansel
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%type <integer> regtype srcimmtype execsize dstregion
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%type <integer> subregnum sampler_datatype
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%type <integer> urb_swizzle urb_allocate urb_used urb_complete
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@ -111,7 +113,8 @@
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%type <direct_reg> dstoperandex_typed srcarchoperandex_typed
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%type <integer> mask_subreg maskstack_subreg maskstackdepth_subreg
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%type <imm32> imm32
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%type <src_operand> directsrcoperand srcarchoperandex directsrcaccoperand
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%type <src_operand> src srcimm imm32reg payload srcacc srcaccimm swizzle
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%%
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ROOT: instrseq
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@ -164,9 +167,10 @@ unaryinstruction:
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$$.header.destreg__conditionalmod = $3;
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$$.header.saturate = $4;
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$$.header.execution_size = $5;
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set_instruction_dest(&$$, &$6);
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set_instruction_src0(&$$, &$7);
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set_instruction_options(&$$, &$8);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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}
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;
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@ -182,10 +186,12 @@ binaryinstruction:
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$$.header.destreg__conditionalmod = $3;
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$$.header.saturate = $4;
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$$.header.execution_size = $5;
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set_instruction_dest(&$$, &$6);
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set_instruction_src0(&$$, &$7);
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set_instruction_src1(&$$, &$8);
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set_instruction_options(&$$, &$9);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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YYERROR;
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}
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;
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@ -201,10 +207,12 @@ binaryaccinstruction:
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$$.header.destreg__conditionalmod = $3;
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$$.header.saturate = $4;
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$$.header.execution_size = $5;
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set_instruction_dest(&$$, &$6);
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set_instruction_src0(&$$, &$7);
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set_instruction_src1(&$$, &$8);
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set_instruction_options(&$$, &$9);
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set_instruction_dest(&$$, &$6);
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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if (set_instruction_src1(&$$, &$8) != 0)
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YYERROR;
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}
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;
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@ -231,7 +239,8 @@ sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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$$.header.execution_size = $3;
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$$.header.destreg__conditionalmod = $4; /* msg reg index */
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set_instruction_dest(&$$, &$5);
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set_instruction_src0(&$$, &$6);
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if (set_instruction_src0(&$$, &$6) != 0)
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YYERROR;
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$$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D;
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$$.bits3.generic = $7.bits3.generic;
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@ -472,33 +481,39 @@ srcimm: directsrcoperand | imm32reg
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imm32reg: imm32 srcimmtype
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{
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$$.bits1.da1.src0_reg_file = BRW_IMMEDIATE_VALUE;
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$$.bits1.da1.src0_reg_type = $2;
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union {
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int i;
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float f;
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} intfloat;
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$$.reg_file = BRW_IMMEDIATE_VALUE;
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$$.reg_type = $2;
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switch ($2) {
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case BRW_REGISTER_TYPE_UD:
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$$.bits3.ud = $1;
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$$.imm32 = $1;
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break;
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case BRW_REGISTER_TYPE_D:
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$$.bits3.id = $1;
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$$.imm32 = $1;
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break;
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case BRW_REGISTER_TYPE_UW:
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$$.bits3.ud = $1;
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$$.imm32 = $1;
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break;
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case BRW_REGISTER_TYPE_W:
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$$.bits3.id = $1;
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$$.imm32 = $1;
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break;
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case BRW_REGISTER_TYPE_UB:
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$$.bits3.ud = $1;
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/* There is no native byte immediate type */
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$$.bits1.da1.src0_reg_type = BRW_REGISTER_TYPE_UD;
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$$.imm32 = (unsigned int)$1;
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$$.reg_type = BRW_REGISTER_TYPE_UD;
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break;
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case BRW_REGISTER_TYPE_B:
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$$.bits3.id = $1;
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/* There is no native byte immediate type */
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$$.bits1.da1.src0_reg_type = BRW_REGISTER_TYPE_D;
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$$.imm32 = (int)$1;
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$$.reg_type = BRW_REGISTER_TYPE_D;
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break;
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case BRW_REGISTER_TYPE_F:
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$$.bits3.fd = $1;
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intfloat.f = $1;
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$$.imm32 = intfloat.i;
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break;
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default:
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fprintf(stderr, "unknown immediate type %d\n", $2);
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@ -517,15 +532,15 @@ directsrcaccoperand: directsrcoperand
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/* Returns a source operand in the src0 fields of an instruction. */
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srcarchoperandex: srcarchoperandex_typed region regtype
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{
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$$.bits1.da1.src0_reg_file = $1.reg_file;
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$$.bits1.da1.src0_reg_type = $3;
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$$.bits2.da1.src0_subreg_nr = $1.subreg_nr;
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$$.bits2.da1.src0_reg_nr = $1.reg_nr;
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$$.bits2.da1.src0_vert_stride = $2.vert_stride;
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$$.bits2.da1.src0_width = $2.width;
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$$.bits2.da1.src0_horiz_stride = $2.horiz_stride;
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$$.bits2.da1.src0_negate = 0;
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$$.bits2.da1.src0_abs = 0;
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$$.reg_file = $1.reg_file;
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$$.reg_type = $3;
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$$.subreg_nr = $1.subreg_nr;
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$$.reg_nr = $1.reg_nr;
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$$.vert_stride = $2.vert_stride;
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$$.width = $2.width;
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$$.horiz_stride = $2.horiz_stride;
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$$.negate = 0;
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$$.abs = 0;
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}
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| maskstackreg
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{
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@ -561,20 +576,22 @@ src: directsrcoperand
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;
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directsrcoperand:
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negate abs directgenreg region regtype
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negate abs directgenreg region regtype swizzle
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{
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/* Returns a source operand in the src0 fields of an
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* instruction.
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*/
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$$.bits1.da1.src0_reg_file = $3.reg_file;
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$$.bits1.da1.src0_reg_type = $5;
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$$.bits2.da1.src0_subreg_nr = $3.subreg_nr;
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$$.bits2.da1.src0_reg_nr = $3.reg_nr;
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$$.bits2.da1.src0_vert_stride = $4.vert_stride;
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$$.bits2.da1.src0_width = $4.width;
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$$.bits2.da1.src0_horiz_stride = $4.horiz_stride;
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$$.bits2.da1.src0_negate = $1;
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$$.bits2.da1.src0_abs = $2;
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$$.reg_file = $3.reg_file;
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$$.reg_nr = $3.reg_nr;
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$$.subreg_nr = $3.subreg_nr;
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$$.reg_type = $5;
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$$.vert_stride = $4.vert_stride;
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$$.width = $4.width;
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$$.horiz_stride = $4.horiz_stride;
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$$.negate = $1;
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$$.abs = $2;
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$$.swizzle_set = $6.swizzle_set;
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$$.swizzle_x = $6.swizzle_x;
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$$.swizzle_y = $6.swizzle_y;
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$$.swizzle_z = $6.swizzle_z;
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$$.swizzle_w = $6.swizzle_w;
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}
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| srcarchoperandex
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;
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@ -812,6 +829,39 @@ regtype: TYPE_F { $$ = BRW_REGISTER_TYPE_F; }
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srcimmtype: regtype
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;
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/* 1.4.10: Swizzle control */
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/* Returns the swizzle control for an align16 instruction's source operand
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* in the src0 fields.
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*/
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swizzle: /* empty */
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{
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$$.swizzle_set = 0;
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$$.swizzle_x = BRW_CHANNEL_X;
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$$.swizzle_y = BRW_CHANNEL_Y;
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$$.swizzle_z = BRW_CHANNEL_Z;
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$$.swizzle_w = BRW_CHANNEL_W;
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}
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| DOT chansel
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{
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$$.swizzle_set = 1;
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$$.swizzle_x = $2;
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$$.swizzle_y = $2;
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$$.swizzle_z = $2;
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$$.swizzle_w = $2;
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}
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| DOT chansel chansel chansel chansel
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{
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$$.swizzle_set = 1;
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$$.swizzle_x = $2;
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$$.swizzle_y = $3;
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$$.swizzle_z = $4;
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$$.swizzle_w = $5;
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}
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;
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chansel: X | Y | Z | W
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;
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/* 1.4.11: Immediate values */
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imm32: INTEGER { $$ = $1; }
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| NUMBER { $$ = $1; }
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@ -939,52 +989,95 @@ void set_instruction_dest(struct brw_instruction *instr,
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instr->bits1.da1.dest_address_mode = dest->bits1.da1.dest_address_mode;
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}
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void set_instruction_src0(struct brw_instruction *instr,
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struct brw_instruction *src)
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/* Sets the first source operand for the instruction. Returns 0 on success. */
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int set_instruction_src0(struct brw_instruction *instr,
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struct src_operand *src)
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{
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instr->bits1.da1.src0_reg_file = src->bits1.da1.src0_reg_file;
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instr->bits1.da1.src0_reg_type = src->bits1.da1.src0_reg_type;
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if (src->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) {
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instr->bits3.ud = src->bits3.ud;
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instr->bits1.da1.src0_reg_file = src->reg_file;
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instr->bits1.da1.src0_reg_type = src->reg_type;
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if (src->reg_file == BRW_IMMEDIATE_VALUE) {
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instr->bits3.ud = src->imm32;
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} else if (instr->header.access_mode == BRW_ALIGN_1) {
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instr->bits2.da1.src0_subreg_nr = src->subreg_nr;
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instr->bits2.da1.src0_reg_nr = src->reg_nr;
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instr->bits2.da1.src0_vert_stride = src->vert_stride;
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instr->bits2.da1.src0_width = src->width;
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instr->bits2.da1.src0_horiz_stride = src->horiz_stride;
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instr->bits2.da1.src0_negate = src->negate;
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instr->bits2.da1.src0_abs = src->abs;
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instr->bits2.da1.src0_address_mode = src->address_mode;
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if (src->swizzle_set) {
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fprintf(stderr, "error: swizzle bits set in align1 "
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"instruction\n");
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return 1;
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}
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} else {
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instr->bits2.da1.src0_subreg_nr =
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src->bits2.da1.src0_subreg_nr;
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instr->bits2.da1.src0_reg_nr = src->bits2.da1.src0_reg_nr;
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instr->bits2.da1.src0_vert_stride =
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src->bits2.da1.src0_vert_stride;
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instr->bits2.da1.src0_width = src->bits2.da1.src0_width;
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instr->bits2.da1.src0_horiz_stride =
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src->bits2.da1.src0_horiz_stride;
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instr->bits2.da1.src0_negate = src->bits2.da1.src0_negate;
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instr->bits2.da1.src0_abs = src->bits2.da1.src0_abs;
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instr->bits2.da16.src0_subreg_nr = src->subreg_nr;
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instr->bits2.da16.src0_reg_nr = src->reg_nr;
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instr->bits2.da16.src0_vert_stride = src->vert_stride;
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instr->bits2.da16.src0_negate = src->negate;
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instr->bits2.da16.src0_abs = src->abs;
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instr->bits2.da16.src0_swz_x = src->swizzle_x;
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instr->bits2.da16.src0_swz_y = src->swizzle_y;
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instr->bits2.da16.src0_swz_z = src->swizzle_z;
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instr->bits2.da16.src0_swz_w = src->swizzle_w;
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instr->bits2.da16.src0_address_mode = src->address_mode;
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}
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return 0;
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}
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void set_instruction_src1(struct brw_instruction *instr,
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struct brw_instruction *src)
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/* Sets the second source operand for the instruction. Returns 0 on success.
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*/
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int set_instruction_src1(struct brw_instruction *instr,
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struct src_operand *src)
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{
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instr->bits1.da1.src1_reg_file = src->bits1.da1.src0_reg_file;
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instr->bits1.da1.src1_reg_type = src->bits1.da1.src0_reg_type;
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if (src->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) {
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instr->bits3.ud = src->bits3.ud;
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instr->bits1.da1.src1_reg_file = src->reg_file;
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instr->bits1.da1.src1_reg_type = src->reg_type;
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if (src->reg_file == BRW_IMMEDIATE_VALUE) {
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instr->bits3.ud = src->imm32;
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} else if (instr->header.access_mode == BRW_ALIGN_1) {
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instr->bits3.da1.src1_subreg_nr = src->subreg_nr;
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instr->bits3.da1.src1_reg_nr = src->reg_nr;
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instr->bits3.da1.src1_vert_stride = src->vert_stride;
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instr->bits3.da1.src1_width = src->width;
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instr->bits3.da1.src1_horiz_stride = src->horiz_stride;
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instr->bits3.da1.src1_negate = src->negate;
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instr->bits3.da1.src1_abs = src->abs;
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if (src->address_mode != BRW_ADDRESS_DIRECT) {
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fprintf(stderr, "error: swizzle bits set in align1 "
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"instruction\n");
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return 1;
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}
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if (src->swizzle_set) {
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fprintf(stderr, "error: swizzle bits set in align1 "
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"instruction\n");
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return 1;
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}
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} else {
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instr->bits3.da1.src1_subreg_nr =
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src->bits2.da1.src0_subreg_nr;
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instr->bits3.da1.src1_reg_nr = src->bits2.da1.src0_reg_nr;
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instr->bits3.da1.src1_vert_stride =
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src->bits2.da1.src0_vert_stride;
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instr->bits3.da1.src1_width = src->bits2.da1.src0_width;
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instr->bits3.da1.src1_horiz_stride =
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src->bits2.da1.src0_horiz_stride;
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instr->bits3.da1.src1_negate = src->bits2.da1.src0_negate;
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instr->bits3.da1.src1_abs = src->bits2.da1.src0_abs;
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instr->bits3.da16.src1_subreg_nr = src->subreg_nr;
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instr->bits3.da16.src1_reg_nr = src->reg_nr;
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instr->bits3.da16.src1_vert_stride = src->vert_stride;
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instr->bits3.da16.src1_negate = src->negate;
|
||||
instr->bits3.da16.src1_abs = src->abs;
|
||||
instr->bits3.da16.src1_swz_x = src->swizzle_x;
|
||||
instr->bits3.da16.src1_swz_y = src->swizzle_y;
|
||||
instr->bits3.da16.src1_swz_z = src->swizzle_z;
|
||||
instr->bits3.da16.src1_swz_w = src->swizzle_w;
|
||||
if (src->address_mode != BRW_ADDRESS_DIRECT) {
|
||||
fprintf(stderr, "error: swizzle bits set in align1 "
|
||||
"instruction\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void set_instruction_options(struct brw_instruction *instr,
|
||||
struct brw_instruction *options)
|
||||
{
|
||||
/* XXX: more instr options */
|
||||
instr->header.access_mode = options->header.access_mode;
|
||||
instr->header.mask_control = options->header.mask_control;
|
||||
instr->header.dependency_control = options->header.dependency_control;
|
||||
@ -992,16 +1085,17 @@ void set_instruction_options(struct brw_instruction *instr,
|
||||
options->header.compression_control;
|
||||
}
|
||||
|
||||
void set_src_operand(struct brw_instruction *instr, struct gen_reg *reg,
|
||||
void set_src_operand(struct src_operand *src, struct gen_reg *reg,
|
||||
int type)
|
||||
{
|
||||
instr->bits1.da1.src0_reg_file = reg->reg_file;
|
||||
instr->bits1.da1.src0_reg_type = type;
|
||||
instr->bits2.da1.src0_subreg_nr = reg->subreg_nr;
|
||||
instr->bits2.da1.src0_reg_nr = reg->reg_nr;
|
||||
instr->bits2.da1.src0_vert_stride = 0;
|
||||
instr->bits2.da1.src0_width = 0;
|
||||
instr->bits2.da1.src0_horiz_stride = 1;
|
||||
instr->bits2.da1.src0_negate = 0;
|
||||
instr->bits2.da1.src0_abs = 0;
|
||||
bzero(src, sizeof(*src));
|
||||
src->reg_file = reg->reg_file;
|
||||
src->reg_type = type;
|
||||
src->subreg_nr = reg->subreg_nr;
|
||||
src->reg_nr = reg->reg_nr;
|
||||
src->vert_stride = 0;
|
||||
src->width = 0;
|
||||
src->horiz_stride = 1;
|
||||
src->negate = 0;
|
||||
src->abs = 0;
|
||||
}
|
||||
|
||||
@ -239,6 +239,24 @@ int saved_state = INITIAL;
|
||||
"signed" { return SIGNED; }
|
||||
"scalar" { return SCALAR; }
|
||||
|
||||
/* channel selectors */
|
||||
"x" {
|
||||
yylval.integer = BRW_CHANNEL_X;
|
||||
return X;
|
||||
}
|
||||
"y" {
|
||||
yylval.integer = BRW_CHANNEL_Y;
|
||||
return Y;
|
||||
}
|
||||
"z" {
|
||||
yylval.integer = BRW_CHANNEL_Z;
|
||||
return Z;
|
||||
}
|
||||
"w" {
|
||||
yylval.integer = BRW_CHANNEL_W;
|
||||
return W;
|
||||
}
|
||||
|
||||
[0-9]* {
|
||||
yylval.integer = atoi(yytext);
|
||||
return INTEGER;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user