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89 Commits

Author SHA1 Message Date
Damien Lespiau
668e0dff7d assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cache 
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:36 +00:00
Damien Lespiau
31259c5edc assembler: Rename three_src_gen6 to da3src 
Mesa's brw_structs.h has named/renamed this field to da3src. Sync with
them.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:36 +00:00
Damien Lespiau
e71f1d2ad4 assembler: Sync brw_instruction's header with mesa's 
Two changes there, a field has been renamed and one bit of padding is
now used for compressed instructions.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:35 +00:00
Damien Lespiau
191c85976d build: Integrate the merged gen assembler in the build system 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:35 +00:00
Eric Anholt
9b40c3724a Add autotools build system, and rearrange directory layout. 2013-03-04 15:54:23 +00:00
Eric Anholt
2d298742bf Add support for register-indirect addressing in source operands. 2013-03-04 15:54:23 +00:00
Eric Anholt
3bcf6b29cd Add support for register-indirect access in destination registers. 
This is untested.  Also, a few bits for source operand register-indirect access
sneak in with this commit.
 2013-03-04 15:54:23 +00:00
Eric Anholt
2dac0a19a4 Add support for destination writemasks. 
This involved changing dest operands to have their own structure like src
operands, as the destination writemask (which is align16-only) shares space
with register numbers in align1 mode.
 2013-03-04 15:54:23 +00:00
Eric Anholt
de1a889fe3 Avoid shift/reduce conflict in predicate by making flagreg and subreg 1 token. 
Thanks to keithp for pointing out where the conflict was.
 2013-03-04 15:54:23 +00:00
Eric Anholt
0ed5d93cc2 Add support for predicate control. 
This is untested on programs using predicate control, and also causes a
shift/reduce conflict.
 2013-03-04 15:54:22 +00:00
Eric Anholt
6a88ada7e8 Add support for swizzle control on source operands. 
This required restructuring to store source operands in a new structure rather
than being stored in instructions, as swizzle is align16-only and shares
storage with other fields for align1 mode.

These changes were not tested on real programs using swizzle.
 2013-03-04 15:54:22 +00:00
Eric Anholt
2a0f135784 Add acc[01] as src operands. 2013-03-04 15:54:22 +00:00
Eric Anholt
edc82a045c Comment cleanup and add missing semicolons after rules. 2013-03-04 15:54:22 +00:00
Eric Anholt
908f37d92d Add support for more instruction options. 2013-03-04 15:54:22 +00:00
Eric Anholt
6db54d7465 Typo fix in comment. 2013-03-04 15:54:22 +00:00
Eric Anholt
1d7d04228e Rename direct_gen_reg struct to direct_reg now that it fills more roles. 2013-03-04 15:54:22 +00:00
Eric Anholt
5297b2a7e8 Support src ARF operands in another place, and spell it arch instead of acc. 2013-03-04 15:54:22 +00:00
Eric Anholt
2c7876583e Add support for more registers as source operands. 2013-03-04 15:54:22 +00:00
Eric Anholt
883408eab8 Add rules for more registers, and use some for destinations. 2013-03-04 15:54:22 +00:00
Eric Anholt
f914c6ace2 Add many more opcodes. 2013-03-04 15:54:22 +00:00
Eric Anholt
569990bf6b Lex the register number with the register name. 
This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW
being lexed as GENREG NUMBER LANGLE etc. rather than
GENREG INTEGER DOT INTEGER LANGLE etc.
 2013-03-04 15:54:22 +00:00
Eric Anholt
3d36079ae3 Add syntax for extended math send functions, and adjust packed_yuv_sf for it. 2013-03-04 15:54:22 +00:00
Eric Anholt
e865196a9d Add a syntax for urb write messages. 2013-03-04 15:54:21 +00:00
Eric Anholt
43313946e7 Add syntax for translating the DP write send message. 2013-03-04 15:54:21 +00:00
Eric Anholt
16324215b2 Fix respecting of instruction options (misunderstood default action behavior). 2013-03-04 15:54:21 +00:00
Eric Anholt
56c4ccfc19 Fix up sampler send message translation and give it a near-usable syntax. 2013-03-04 15:54:21 +00:00
Eric Anholt
e609d6ba93 Zero out the initial header instoptions. 2013-03-04 15:54:21 +00:00
Eric Anholt
56b50b6803 bzero instructions before filling in the bits we care about. 
This avoids some set bits in padding fields.
 2013-03-04 15:54:21 +00:00
Eric Anholt
7c330fbf3a Fill in type of null register to match Mesa. 2013-03-04 15:54:21 +00:00
Eric Anholt
a34d1e0d8c Fix translation of message registers. 2013-03-04 15:54:21 +00:00
Eric Anholt
90aea51983 Fix translation of saturate value, and wire conditionalmod to 0 for now. 2013-03-04 15:54:21 +00:00
Eric Anholt
dc96c56d9e Add support for negate and abs to source operands. 2013-03-04 15:54:21 +00:00
Eric Anholt
0d929b430b Fix imm32 translation. 2013-03-04 15:54:20 +00:00
Eric Anholt
0edcb2561d Fix dest_horiz_stride translation, and destination type. 2013-03-04 15:54:20 +00:00
Eric Anholt
d4c82e8278 Fix horizontal stride translation. 2013-03-04 15:54:20 +00:00
Eric Anholt
f2f18561e5 C warnings cleanup. 2013-03-04 15:54:20 +00:00
Eric Anholt
19f1c1cec4 Start correcting the translation. 2013-03-04 15:54:20 +00:00
Eric Anholt
6c98c8d578 Get the wm program to parse. 2013-03-04 15:54:20 +00:00
Eric Anholt
22a1063cc0 Initial gen4asm code. 2013-03-04 15:54:20 +00:00