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assembler: Sync brw_instruction's header with mesa's

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Two changes there, a field has been renamed and one bit of padding is
now used for compressed instructions.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Damien Lespiau 2013-01-14 19:13:19 +00:00
parent 5d52689939
commit e71f1d2ad4
3 changed files with 38 additions and 34 deletions
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34
assembler/brw_structs.h
View File

@ -1043,21 +1043,25 @@ struct brw_instruction
{
struct
{
GLuint opcode:7; /* 0x0000007f */
GLuint pad:1; /* 0x00000080 */ /* reserved for Opcode */
GLuint access_mode:1; /* 0x00000100 */
GLuint mask_control:1; /* 0x00000200 */
GLuint dependency_control:2; /* 0x00000c00 */
GLuint compression_control:2; /* 0x00003000 */
GLuint thread_control:2; /* 0x0000c000 */
GLuint predicate_control:4; /* 0x000f0000 */
GLuint predicate_inverse:1; /* 0x00100000 */
GLuint execution_size:3; /* 0x00e00000 */
GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */
GLuint acc_wr_control:1; /* 0x10000000 */
GLuint pad0:1; /* 0x20000000 */
GLuint debug_control:1; /* 0x40000000 */
GLuint saturate:1; /* 0x80000000 */
GLuint opcode:7;
GLuint pad:1;
GLuint access_mode:1;
GLuint mask_control:1;
GLuint dependency_control:2;
GLuint compression_control:2; /* gen6: quater control */
GLuint thread_control:2;
GLuint predicate_control:4;
GLuint predicate_inverse:1;
GLuint execution_size:3;
/**
* Conditional Modifier for most instructions. On Gen6+, this is also
* used for the SEND instruction's Message Target/SFID.
*/
GLuint destreg__conditionalmod:4;
GLuint acc_wr_control:1;
GLuint cmpt_control:1;
GLuint debug_control:1;
GLuint saturate:1;
} header;
union {

8
assembler/disasm.c
View File

@ -798,7 +798,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
if (inst->header.opcode != BRW_OPCODE_SEND &&
inst->header.opcode != BRW_OPCODE_SENDC)
err |= control (file, "conditional modifier", conditional_modifier,
inst->header.sfid_destreg__conditionalmod, NULL);
inst->header.destreg__conditionalmod, NULL);
if (inst->header.opcode != BRW_OPCODE_NOP) {
string (file, "(");
@ -808,7 +808,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
if (inst->header.opcode == BRW_OPCODE_SEND ||
inst->header.opcode == BRW_OPCODE_SENDC)
format (file, " %d", inst->header.sfid_destreg__conditionalmod);
format (file, " %d", inst->header.destreg__conditionalmod);
if (opcode[inst->header.opcode].ndst > 0) {
pad (file, 16);
@ -829,8 +829,8 @@ int disasm (FILE *file, struct brw_instruction *inst)
pad (file, 16);
space = 0;
err |= control (file, "target function", target_function,
inst->header.sfid_destreg__conditionalmod, &space);
switch (inst->header.sfid_destreg__conditionalmod) {
inst->header.destreg__conditionalmod, &space);
switch (inst->header.destreg__conditionalmod) {
case BRW_MESSAGE_TARGET_MATH:
err |= control (file, "math function", math_function,
inst->bits3.math.function, &space);

30
assembler/gram.y
View File

@ -678,7 +678,7 @@ unaryinstruction:
{
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.sfid_destreg__conditionalmod = $3.cond;
$$.header.destreg__conditionalmod = $3.cond;
$$.header.saturate = $4;
$$.header.execution_size = $5;
set_instruction_options(&$$, &$8);
@ -715,7 +715,7 @@ binaryinstruction:
{
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.sfid_destreg__conditionalmod = $3.cond;
$$.header.destreg__conditionalmod = $3.cond;
$$.header.saturate = $4;
$$.header.execution_size = $5;
set_instruction_options(&$$, &$9);
@ -754,7 +754,7 @@ binaryaccinstruction:
{
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.sfid_destreg__conditionalmod = $3.cond;
$$.header.destreg__conditionalmod = $3.cond;
$$.header.saturate = $4;
$$.header.execution_size = $5;
set_instruction_options(&$$, &$9);
@ -801,7 +801,7 @@ trinaryinstruction:
$$.bits1.three_src_gen6.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr;
$$.header.opcode = $2;
$$.header.sfid_destreg__conditionalmod = $3.cond;
$$.header.destreg__conditionalmod = $3.cond;
$$.header.saturate = $4;
$$.header.execution_size = $5;
@ -839,7 +839,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */
$$.header.destreg__conditionalmod = $4; /* msg reg index */
set_instruction_predicate(&$$, &$1);
if (set_instruction_dest(&$$, &$5) != 0)
YYERROR;
@ -869,9 +869,9 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
if (IS_GENp(5)) {
if (IS_GENp(6)) {
$$.header.sfid_destreg__conditionalmod = $7.bits2.send_gen5.sfid;
$$.header.destreg__conditionalmod = $7.bits2.send_gen5.sfid;
} else {
$$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */
$$.header.destreg__conditionalmod = $4; /* msg reg index */
$$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid;
$$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread;
}
@ -882,7 +882,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
$$.bits3.generic_gen5.end_of_thread =
$12.bits3.generic_gen5.end_of_thread;
} else {
$$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */
$$.header.destreg__conditionalmod = $4; /* msg reg index */
$$.bits3.generic = $7.bits3.generic;
$$.bits3.generic.msg_length = $9;
$$.bits3.generic.response_length = $11;
@ -895,7 +895,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */
$$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */
set_instruction_predicate(&$$, &$1);
@ -918,7 +918,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */
$$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */
set_instruction_predicate(&$$, &$1);
if (set_instruction_dest(&$$, &$4) != 0)
@ -948,7 +948,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
$$.header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
set_instruction_predicate(&$$, &$1);
if (set_instruction_dest(&$$, &$4) != 0)
@ -994,7 +994,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
$$.header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
set_instruction_predicate(&$$, &$1);
if (set_instruction_dest(&$$, &$4) != 0)
@ -1029,7 +1029,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */
$$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */
set_instruction_predicate(&$$, &$1);
if (set_instruction_dest(&$$, &$4) != 0)
@ -1051,7 +1051,7 @@ sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.execution_size = $3;
$$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */
$$.header.destreg__conditionalmod = $5.reg_nr; /* msg reg index */
set_instruction_predicate(&$$, &$1);
@ -1100,7 +1100,7 @@ mathinstruction: predicate MATH_INST execsize dst src srcimm math_function insto
{
memset(&$$, 0, sizeof($$));
$$.header.opcode = $2;
$$.header.sfid_destreg__conditionalmod = $7;
$$.header.destreg__conditionalmod = $7;
$$.header.execution_size = $3;
set_instruction_options(&$$, &$8);
set_instruction_predicate(&$$, &$1);