It's time to start converting the emission code in gram.y to use libbrw
infrastructure. Let's start with using brw_reg for declared register.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Until now, the assembler had relocation-related fields added to struct
brw_instruction. This changes the size of the structure and break code
assuming the opcode structure is really 16 bytes, for instance the
emission code in brw_eu_emit.c.
With this commit, we build on the infrastructure that slowly emerged in
the few previous commits to add a relocatable instruction with the
needed fields.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The output of the parsing is a list of struct brw_program_instruction.
These instructions can be either GEN instructions aka struct
brw_instruction or labels. To make this more explicit we now have a type
to test to determine which instruction we are dealing with.
This will also allow to to pull the relocation bits into struct
brw_program_instruction instead of having them in the structure
representing the opcodes.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Factoring out the code from the grammar will allow us to switch to
using brw_compile in a cleaner way.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This function can only be called to resolve subreg_nr in direct mode
(there is an other function for the indirect case) and it makes no sense
to call it with an immediate operand.
Express those facts with asserts and simplify the logic.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Another step towards using struct brw_reg for source and destination
operands.
Instead of having a separate field to store the sub register number of
the address register in indirect access mode, we can reuse the subreg_nr
field that was only used for direct access so far.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
writemask_set gets in the way of switching to using struct brw_reg and
it's possible to derive it from the writemask value.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
We ended up with 2 structures that where exactly the same, so just use
one, which happens to be the one Mesa has.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
I had to drop how mesa splits msg_control as the current assembly
language gives access the the whole msg_control field.
Recompiling the xorg and the intel driver of libva shaders doesn't show
any difference in the assembly created.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
I had to drop how mesa splits msg_control as the current assembly
language gives access the the whole msg_control field.
Recompiling the xorg and the intel driver of libva shaders doesn't show
any difference in the assembly created.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Two changes there, a field has been renamed and one bit of padding is
now used for compressed instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This involved changing dest operands to have their own structure like src
operands, as the destination writemask (which is align16-only) shares space
with register numbers in align1 mode.
This required restructuring to store source operands in a new structure rather
than being stored in instructions, as swizzle is align16-only and shares
storage with other fields for align1 mode.
These changes were not tested on real programs using swizzle.
This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW
being lexed as GENREG NUMBER LANGLE etc. rather than
GENREG INTEGER DOT INTEGER LANGLE etc.
