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85 Commits

Author SHA1 Message Date
Homer Hsing
c56d786116 Make sure Gen6 ENDIF work 2013-03-04 15:54:34 +00:00
Homer Hsing
c91bd8c76f Fix Gen6 ELSE instructions code logic according to bspec. 2013-03-04 15:54:34 +00:00
Homer Hsing
ce55552470 Make sure BREAK/CONT/HALT work on Gen6. 2013-03-04 15:54:34 +00:00
Homer Hsing
3de439e2f5 Support Gen6 RET instruction. 2013-03-04 15:54:34 +00:00
Homer Hsing
7529682d0a Support Gen6 CALL instruction. 2013-03-04 15:54:34 +00:00
Homer Hsing
b899aba57f Replace variable init code in WAIT by src_null_reg 2013-03-04 15:54:34 +00:00
Homer Hsing
7e2461b6fc Let ip_dst and ip_src become local const variable, so as to reduce replicated code. 2013-03-04 15:54:34 +00:00
Homer Hsing
45ab3cf5a1 Support Gen6 three-source-operand instructions. 
Add bits1.three_src.gen6.dest_reg_file according to Gen6 spec
 2013-03-04 15:54:33 +00:00
Homer Hsing
72a3c194db Compile ELSE and WHILE in Gen5 as same way as in Gen4 2013-03-04 15:54:33 +00:00
Homer Hsing
4bf84ec146 Fully support Gen7 branching instructions 
Also fix integer argument parsing rule for JMPI, IF and WHILE
Fix shift/reduce conflicts in relativelocation
 2013-03-04 15:54:33 +00:00
Homer Hsing
88dfdf34df Supporting multi-branch instructios BRD & BRC 
brd: redirect channels to branches
brc: let channels converging together

also rewrite code converting label to offset
 2013-03-04 15:54:33 +00:00
Homer Hsing
5d589dbe13 Use right-recursing in parser rule inst_option_list 
This recursing cost less memory. It is recommended by Bison.
 2013-03-04 15:54:33 +00:00
Homer Hsing
a7b1c09d18 Support subroutine instructions, CALL & RET 2013-03-04 15:54:33 +00:00
Homer Hsing
c0ebde2786 Merge replicative code in gram.y 2013-03-04 15:54:33 +00:00
Homer Hsing
b0b540f02a Reduce replicative code in gram.y by reloc_target field in src_operand 
Bspec says JIP and UIP should be the source operands. It is better if
src_operand has a field "reloc_target" according to bspec.
The replicative code in JMPI and branchloop rules can be merged into one.
 2013-03-04 15:54:33 +00:00
Homer Hsing
1f9a4d71e8 Restrict type of relativelocation2 to int 
Original rule set it to EXP | NUMBER, then YYERROR if it is NUMBER.
This patch set it directly to EXP, restricting its type to int.
 2013-03-04 15:54:33 +00:00
Homer Hsing
751838e809 Add second_reloc_target in the data structure. 
Since Gen6+, some branching instructions have two relocation targets.
 2013-03-04 15:54:33 +00:00
Homer Hsing
2ab4c0d9b8 Fix memory leaking in the parser 
STRING has been malloc'ed by strdup in src/lex.l but forgotten to
be freed in src/gram.y.
 2013-03-04 15:54:33 +00:00
Homer Hsing
bebe8179e1 According to BSPEC, put PLN & BFI1 to binaryop, put SUBB to binaryaccop 
bspec: BFI1 should not access accumulator. PLN should not use accumulator
as source.
future work in gram.y: show warning if acc is used as dest for
ADDC/SUBB/CMP/CMPN/SHL/BFI1.
 2013-03-04 15:54:32 +00:00
Homer Hsing
74383f4db4 Explain the difference between binaryinstruction and binaryaccinstruction 
Developers may add new instructions in wrong place in the future
if they don't know the difference between binaryinstruction and
binaryaccinstruction.
 2013-03-04 15:54:32 +00:00
Homer Hsing
e6d61ac202 Merge same if branches in declare_pragma section in gram.y 2013-03-04 15:54:32 +00:00
Homer Hsing
81859af110 Replace bzero by memset. 
bzero has been removed from POSIX.1-2008. Should use memset instead.
 2013-03-04 15:54:31 +00:00
Homer Hsing
b1ef3bc209 Supporting integer subtraction with borrow 
subb: subtract unsigned integer src1 from src0. store the result
in dst and store the borrow (0 or 1) as a 32-bit value in acc.
 2013-03-04 15:54:31 +00:00
Homer Hsing
9e711a4f2c Supporting find first bit instructions 
fbh: Find the first significant bit searching from the high bits
in src0 and store the result in dst.

fbl: Find the first 1 bit searching from the low bits in src0
and store the result in dst.
 2013-03-04 15:54:31 +00:00
Homer Hsing
b094cd8648 Supporting half precision to single precision float convertion 
The f16to32 instruction converts the half precision float
in src0 to single precision float and storing in dst.

The f32to16 instruction converts the single precision float
in src0 to half precision float and storing in the lower word
of each channel in dst.
 2013-03-04 15:54:31 +00:00
Homer Hsing
4285d9c2ce Supporting count bit set instruction 
The cbit instruction counts component-wise the total bits set
in src0 and stores the resulting counts in dst.
 2013-03-04 15:54:31 +00:00
Homer Hsing
d4f48a7271 Supporting instruction "reverse bits" 
The bfrev instruction component-wise reverses all the bits in src0
and stores the results in dst.
 2013-03-04 15:54:31 +00:00
Homer Hsing
4d6337dfaf Supporting instruction Bit Field Insert 1 
The bfi1 instruction component-wise generates mask with control
from src0 and src1 and stores the results in dst.
 2013-03-04 15:54:31 +00:00
Homer Hsing
c3f1e0a732 Supporting addc instruction 
The addc instruction performs component-wise addition of
src0 and src1 and stores the results in dst;
it also stores the carry into acc.
 2013-03-04 15:54:31 +00:00
Homer Hsing
8ca55688ea Supporting bit field extract and bit field insert 2 
Supporting two new operators, bfe and bfi2
bfe: Component-wise extracts a bit field from src2 using the bit field width from src0 and the bit field offset from src1.
bfi2: component-wise performs the bitfield insert operation on src1 and src2 based on the mask in src0.
 2013-03-04 15:54:31 +00:00
Homer Hsing
210510cebb Supporting LRP: dest = src0 * src1 + (1-src0) * src2 2013-03-04 15:54:31 +00:00
Homer Hsing
a034bcbd04 Support trinary source instruction "multiply add". 
MAD (Multiply ADd) computes dst <- src1*src2 + src0.

Tried best to follow previous variable naming habit.

Also renamed "triinstruction" -> "trinaryinstruction" in grammar parser
for better readability.
 2013-03-04 15:54:31 +00:00
Xiang, Haihao
4d75db550e Waring if both predication and conditional modifier are enabled but use different flag registers 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
3ffbe96c1e Add support for flag register f1 on Ivy bridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
2f772dd67b s/flag_reg_nr/flag_subreg_nr for an instruction 
s/flagreg/flag_subreg_nr for a condition

They are flag subregister number indeed

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
f3f6ba24e6 Change the rule for flag register 
The shift/reduce conflict mentioned in the comment has been fixed, so
flagreg can return the reg number in the lvalue now. In addition, it will
be easy to add support for flag register f1 on Ivy bridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
128053f120 Accept symbol register as the leading register of the request 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
0b5f7fa049 A new syntax of SEND intruction on Ivybridge 
[(<pred>)] send (<exec_size>) reg greg imm6 reg32a

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
86f8ca6af9 Support VME on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
27050395d2 Support DP for sampler/render/constant/data cache 
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
e97f0bca5f sampler/render/constant cache unit since Sandybridge 
since Sandybrdige, there isn't a single function unit for data port read/write.
Instead sampler/render/constant cache unit is introduced, data port read/write
can be specified in a SEND instruction with different cache unit. To keep compatibility,
currently data port read always uses sampler cache unit however data port write
uses render cache unit

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
6a3a9e7148 fix an error in commit cf76278 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
46ffdd5df7 SEND uses GRFs instead of MRFs on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
67d4ed665d Add support for sample (00000) on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
c8d6bf353e Add support for data port read/write on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Feng, Boqun
37d68103a8 Send instruction on PRE-ILK 
[(<pred>)] send (<exec_size>) <pdst> <cdst> <src0> <desc>
 2013-03-04 15:54:28 +00:00
Zhou Chang
52399867bf Add VME support in SEND 2013-03-04 15:54:28 +00:00
Xiang, Haihao
e7f4dc6e39 fix the parameters of register region 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
85da7b9e8a send instruction on GEN6 
[(<pred>)] send (<exec_size>) reg mreg imm6 imm32

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
852216d6e3 fix notification count register 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00