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Support DP for sampler/render/constant/data cache

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Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
This commit is contained in:
Xiang, Haihao 2011-06-10 16:04:30 +08:00 committed by Damien Lespiau
parent e97f0bca5f
commit 27050395d2
4 changed files with 54 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
assembler/src/brw_defines.h
View File

@ -711,6 +711,7 @@
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7
#define BRW_MESSAGE_TARGET_VME 8
#define BRW_MESSAGE_TARGET_DP_CC 9 /* data port constant cache */
#define BRW_MESSAGE_TARGET_DP_DC 10 /* data port data cache */
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2

15
assembler/src/brw_structs.h
View File

@ -1453,11 +1453,24 @@ struct brw_instruction
GLuint end_of_thread:1;
} dp_write_gen6;
struct {
GLuint binding_table_index:8;
GLuint msg_control:5;
GLuint msg_type:4;
GLuint send_commit_msg:1; /* ignore on read message */
GLuint pad0:1;
GLuint header_present:1;
GLuint response_length:5;
GLuint msg_length:4;
GLuint pad1:2;
GLuint end_of_thread:1;
} dp_gen6;
struct {
GLuint binding_table_index:8;
GLuint msg_control:6;
GLuint msg_type:4;
GLuint pad0:1;
GLuint category:1;
GLuint header_present:1;
GLuint response_length:5;
GLuint msg_length:4;

39
assembler/src/gram.y
View File

@ -111,7 +111,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
%token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL
%token <integer> MATH_INST
%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME
%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME DATA_PORT
%token MSGLEN RETURNLEN
%token <integer> ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE
@ -1212,6 +1212,43 @@ msgtarget: NULL_TOKEN
YYERROR;
}
}
| DATA_PORT LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA
INTEGER COMMA INTEGER COMMA INTEGER RPAREN
{
$$.bits2.send_gen5.sfid = $3;
$$.bits3.generic_gen5.header_present = ($13 != 0);
if (gen_level >= 7) {
if ($3 != BRW_MESSAGE_TARGET_DP_SC &&
$3 != BRW_MESSAGE_TARGET_DP_RC &&
$3 != BRW_MESSAGE_TARGET_DP_CC &&
$3 != BRW_MESSAGE_TARGET_DP_DC) {
fprintf (stderr, "error: wrong cache type\n");
YYERROR;
}
$$.bits3.dp_gen7.category = $11;
$$.bits3.dp_gen7.binding_table_index = $9;
$$.bits3.dp_gen7.msg_control = $7;
$$.bits3.dp_gen7.msg_type = $5;
} else if (gen_level == 6) {
if ($3 != BRW_MESSAGE_TARGET_DP_SC &&
$3 != BRW_MESSAGE_TARGET_DP_RC &&
$3 != BRW_MESSAGE_TARGET_DP_CC) {
fprintf (stderr, "error: wrong cache type\n");
YYERROR;
}
$$.bits3.dp_gen6.send_commit_msg = $11;
$$.bits3.dp_gen6.binding_table_index = $9;
$$.bits3.dp_gen6.msg_control = $7;
$$.bits3.dp_gen6.msg_type = $5;
} else if (gen_level < 5) {
fprintf (stderr, "Gen6- donesn't support data port for sampler/render/constant/data cache\n");
YYERROR;
}
}
;
urb_allocate: ALLOCATE { $$ = 1; }

1
assembler/src/lex.l
View File

@ -137,6 +137,7 @@ yylval.integer = BRW_CHANNEL_W;
"urb" { return URB; }
"thread_spawner" { return THREAD_SPAWNER; }
"vme" { return VME; }
"data_port" { return DATA_PORT; }
"allocate" { return ALLOCATE; }
"used" { return USED; }