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https://github.com/tiagovignatti/intel-gpu-tools.git
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Supporting count bit set instruction
The cbit instruction counts component-wise the total bits set in src0 and stores the resulting counts in dst.
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@ -601,6 +601,7 @@
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#define BRW_OPCODE_MAC 72
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#define BRW_OPCODE_MACH 73
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#define BRW_OPCODE_LZD 74
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#define BRW_OPCODE_CBIT 77
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#define BRW_OPCODE_ADDC 78
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#define BRW_OPCODE_SAD2 80
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#define BRW_OPCODE_SADA2 81
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@ -115,7 +115,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
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%token <integer> MOV FRC RNDU RNDD RNDE RNDZ NOT LZD
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%token <integer> MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2
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%token <integer> AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN
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%token <integer> ADDC BFI1 BFREV
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%token <integer> ADDC BFI1 BFREV CBIT
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%token <integer> SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE
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%token <integer> PUSH MREST POP WAIT DO ENDIF ILLEGAL
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%token <integer> MATH_INST
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@ -417,7 +417,7 @@ unaryinstruction:
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}
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;
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unaryop: MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD | BFREV
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unaryop: MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD | BFREV | CBIT
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;
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binaryinstruction:
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@ -100,6 +100,7 @@ yylval.integer = BRW_CHANNEL_W;
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"dp3" { yylval.integer = BRW_OPCODE_DP3; return DP3; }
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"dp2" { yylval.integer = BRW_OPCODE_DP2; return DP2; }
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"cbit" { yylval.integer = BRW_OPCODE_CBIT; return CBIT; }
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"avg" { yylval.integer = BRW_OPCODE_AVG; return AVG; }
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"add" { yylval.integer = BRW_OPCODE_ADD; return ADD; }
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"addc" { yylval.integer = BRW_OPCODE_ADDC; return ADDC; }
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