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https://github.com/tiagovignatti/intel-gpu-tools.git
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Add support for flag register f1 on Ivy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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2f772dd67b
commit
3ffbe96c1e
@ -1135,7 +1135,8 @@ struct brw_instruction
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GLuint src0_width:3; /* 0x001c0000 */
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GLuint src0_vert_stride:4; /* 0x01e00000 */
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GLuint flag_subreg_nr:1; /* 0x02000000 */
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GLuint pad:6; /* 0xfc000000 */
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GLuint flag_reg_nr:1; /* 0x04000000 */
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GLuint pad:5; /* 0xf8000000 */
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} da1;
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struct
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@ -1149,7 +1150,8 @@ struct brw_instruction
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GLuint src0_width:3;
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GLuint src0_vert_stride:4;
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GLuint flag_subreg_nr:1;
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GLuint pad:6;
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GLuint flag_reg_nr:1;
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GLuint pad:5;
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} ia1;
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struct
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@ -1166,7 +1168,8 @@ struct brw_instruction
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GLuint pad0:1;
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GLuint src0_vert_stride:4;
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GLuint flag_subreg_nr:1;
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GLuint pad1:6;
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GLuint flag_reg_nr:1;
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GLuint pad1:5;
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} da16;
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struct
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@ -1183,7 +1186,8 @@ struct brw_instruction
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GLuint pad0:1;
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GLuint src0_vert_stride:4;
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GLuint flag_subreg_nr:1;
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GLuint pad1:6;
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GLuint flag_reg_nr:1;
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GLuint pad1:5;
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} ia16;
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struct
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@ -779,7 +779,7 @@ int disasm (FILE *file, struct brw_instruction *inst)
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if (inst->header.predicate_control) {
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string (file, "(");
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err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
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string (file, "f0");
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format (file, "f%d", inst->bits2.da1.flag_reg_nr);
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if (inst->bits2.da1.flag_subreg_nr)
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format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
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if (inst->header.access_mode == BRW_ALIGN_1)
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@ -49,6 +49,7 @@ struct direct_reg {
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struct condition {
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int cond;
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int flag_reg_nr;
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int flag_subreg_nr;
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};
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@ -389,8 +389,10 @@ unaryinstruction:
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if (set_instruction_src0(&$$, &$7) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1)
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if ($3.flag_subreg_nr != -1) {
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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}
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if (gen_level < 6 &&
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get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
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@ -419,8 +421,10 @@ binaryinstruction:
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if (set_instruction_src1(&$$, &$8) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1)
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if ($3.flag_subreg_nr != -1) {
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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}
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if (gen_level < 6 &&
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get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
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@ -449,8 +453,10 @@ binaryaccinstruction:
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if (set_instruction_src1(&$$, &$8) != 0)
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YYERROR;
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if ($3.flag_subreg_nr != -1)
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if ($3.flag_subreg_nr != -1) {
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$$.bits2.da1.flag_reg_nr = $3.flag_reg_nr;
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$$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr;
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}
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if (gen_level < 6 &&
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get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64)
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@ -1849,7 +1855,8 @@ accreg: ACCREG subregnum
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flagreg: FLAGREG subregnum
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{
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if ($1 > 0) {
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if ((gen_level <= 6 && $1) > 0 ||
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(gen_level > 6 && $1 > 1)) {
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fprintf(stderr,
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"flag register number %d out of range\n", $1);
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YYERROR;
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@ -2291,6 +2298,7 @@ imm32: exp { $$.r = imm32_d; $$.u.d = $1; }
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predicate: /* empty */
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{
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$$.header.predicate_control = BRW_PREDICATE_NONE;
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$$.bits2.da1.flag_reg_nr = 0;
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$$.bits2.da1.flag_subreg_nr = 0;
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$$.header.predicate_inverse = 0;
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}
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@ -2301,6 +2309,7 @@ predicate: /* empty */
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* set a predicate for one flag register and conditional
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* modification on the other flag register.
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*/
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$$.bits2.da1.flag_reg_nr = ($3.reg_nr & 0xF);
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$$.bits2.da1.flag_subreg_nr = $3.subreg_nr;
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$$.header.predicate_inverse = $2;
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}
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@ -2360,11 +2369,13 @@ saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; }
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conditionalmodifier: condition
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{
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$$.cond = $1;
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$$.flag_reg_nr = 0;
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$$.flag_subreg_nr = -1;
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}
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| condition DOT flagreg
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{
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$$.cond = $1;
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$$.flag_reg_nr = ($3.reg_nr & 0xF);
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$$.flag_subreg_nr = $3.subreg_nr;
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}
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@ -2848,6 +2859,7 @@ void set_instruction_predicate(struct brw_instruction *instr,
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{
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instr->header.predicate_control = predicate->header.predicate_control;
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instr->header.predicate_inverse = predicate->header.predicate_inverse;
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instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr;
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instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr;
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}
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