Eric Anholt
d538dfc462
Fix the width of the IP count field expected by the while test.
2013-03-04 15:54:24 +00:00
Eric Anholt
892d6e7ed0
Fix copy'n'paste-o in lexing of the WHILE instruction.
2013-03-04 15:54:24 +00:00
Eric Anholt
56cdee41af
Initialize the structure used for setting up the ip src/dst in branches/jumps.
...
This fixes jmpi, if, and iff. The while test still fails to compile.
2013-03-04 15:54:24 +00:00
Eric Anholt
8828725dc9
Add tests for jmpi, if, iff, and while, revealing issues.
2013-03-04 15:54:24 +00:00
Eric Anholt
cc865f1bc0
Explain why rnde-intsrc is expected to fail.
2013-03-04 15:54:24 +00:00
Eric Anholt
78cb82a1e2
Add some masks in comments that will help with writing tests.
2013-03-04 15:54:24 +00:00
Eric Anholt
b6fe4bbe2e
Add configure.lineno to ignores.
2013-03-04 15:54:24 +00:00
Eric Anholt
863cd6a5b7
Add more unary operation tests.
2013-03-04 15:54:23 +00:00
Eric Anholt
e3cc73bec4
Start adding a test suite.
2013-03-04 15:54:23 +00:00
Eric Anholt
356ce76d44
Add a rule for the ELSE instruction.
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Untested.
2013-03-04 15:54:23 +00:00
Eric Anholt
1e907c7aed
Add rules for branch and jump instructions.
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Untested.
2013-03-04 15:54:23 +00:00
Eric Anholt
d77712994d
Add DO and ENDIF instructions.
2013-03-04 15:54:23 +00:00
Eric Anholt
74c81af3dd
Fix a compiler warning by defining struct {in,}direct_reg at the top level.
2013-03-04 15:54:23 +00:00
Eric Anholt
cc05ba1d9e
Fix gram.h creation, fixing dependencies and distcheck.
2013-03-04 15:54:23 +00:00
Eric Anholt
c8939edc28
Fix issues in the grammar that caused errors in bison.
2013-03-04 15:54:23 +00:00
Eric Anholt
9b40c3724a
Add autotools build system, and rearrange directory layout.
2013-03-04 15:54:23 +00:00
Eric Anholt
5fbc399062
Add input/output file command line arguments.
2013-03-04 15:54:23 +00:00
Eric Anholt
2d298742bf
Add support for register-indirect addressing in source operands.
2013-03-04 15:54:23 +00:00
Eric Anholt
3bcf6b29cd
Add support for register-indirect access in destination registers.
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This is untested. Also, a few bits for source operand register-indirect access
sneak in with this commit.
2013-03-04 15:54:23 +00:00
Eric Anholt
2dac0a19a4
Add support for destination writemasks.
...
This involved changing dest operands to have their own structure like src
operands, as the destination writemask (which is align16-only) shares space
with register numbers in align1 mode.
2013-03-04 15:54:23 +00:00
Eric Anholt
de1a889fe3
Avoid shift/reduce conflict in predicate by making flagreg and subreg 1 token.
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Thanks to keithp for pointing out where the conflict was.
2013-03-04 15:54:23 +00:00
Eric Anholt
0ed5d93cc2
Add support for predicate control.
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This is untested on programs using predicate control, and also causes a
shift/reduce conflict.
2013-03-04 15:54:22 +00:00
Eric Anholt
6a88ada7e8
Add support for swizzle control on source operands.
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This required restructuring to store source operands in a new structure rather
than being stored in instructions, as swizzle is align16-only and shares
storage with other fields for align1 mode.
These changes were not tested on real programs using swizzle.
2013-03-04 15:54:22 +00:00
Eric Anholt
2a0f135784
Add acc[01] as src operands.
2013-03-04 15:54:22 +00:00
Eric Anholt
edc82a045c
Comment cleanup and add missing semicolons after rules.
2013-03-04 15:54:22 +00:00
Eric Anholt
908f37d92d
Add support for more instruction options.
2013-03-04 15:54:22 +00:00
Eric Anholt
6db54d7465
Typo fix in comment.
2013-03-04 15:54:22 +00:00
Eric Anholt
1d7d04228e
Rename direct_gen_reg struct to direct_reg now that it fills more roles.
2013-03-04 15:54:22 +00:00
Eric Anholt
5297b2a7e8
Support src ARF operands in another place, and spell it arch instead of acc.
2013-03-04 15:54:22 +00:00
Eric Anholt
2c7876583e
Add support for more registers as source operands.
2013-03-04 15:54:22 +00:00
Eric Anholt
883408eab8
Add rules for more registers, and use some for destinations.
2013-03-04 15:54:22 +00:00
Eric Anholt
2cca382cd2
Rename the resulting binary to gen4asm instead of lextest.
2013-03-04 15:54:22 +00:00
Eric Anholt
c81a6084de
Add a negation that the initial disasm missed.
2013-03-04 15:54:22 +00:00
Eric Anholt
f914c6ace2
Add many more opcodes.
2013-03-04 15:54:22 +00:00
Eric Anholt
569990bf6b
Lex the register number with the register name.
...
This avoids the need for a start condition to prevent for example g1.8<0,1,0>UW
being lexed as GENREG NUMBER LANGLE etc. rather than
GENREG INTEGER DOT INTEGER LANGLE etc.
2013-03-04 15:54:22 +00:00
Eric Anholt
3d36079ae3
Add syntax for extended math send functions, and adjust packed_yuv_sf for it.
2013-03-04 15:54:22 +00:00
Eric Anholt
e865196a9d
Add a syntax for urb write messages.
2013-03-04 15:54:21 +00:00
Eric Anholt
5232981c88
Add some more generated files to ignore.
2013-03-04 15:54:21 +00:00
Eric Anholt
bf0b5ddbe7
Add packed yuv sf kernel from 2d driver.
2013-03-04 15:54:21 +00:00
Eric Anholt
43313946e7
Add syntax for translating the DP write send message.
2013-03-04 15:54:21 +00:00
Eric Anholt
16324215b2
Fix respecting of instruction options (misunderstood default action behavior).
2013-03-04 15:54:21 +00:00
Eric Anholt
56c4ccfc19
Fix up sampler send message translation and give it a near-usable syntax.
2013-03-04 15:54:21 +00:00
Eric Anholt
e609d6ba93
Zero out the initial header instoptions.
2013-03-04 15:54:21 +00:00
Eric Anholt
2093218bcd
There's no reason to provide typing or region on the null register.
2013-03-04 15:54:21 +00:00
Eric Anholt
56b50b6803
bzero instructions before filling in the bits we care about.
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This avoids some set bits in padding fields.
2013-03-04 15:54:21 +00:00
Eric Anholt
7c330fbf3a
Fill in type of null register to match Mesa.
2013-03-04 15:54:21 +00:00
Eric Anholt
ac32bb09eb
This code was supposed to be null instead of acc0 (brw_disasm.c gave "a0").
2013-03-04 15:54:21 +00:00
Eric Anholt
a34d1e0d8c
Fix translation of message registers.
2013-03-04 15:54:21 +00:00
Eric Anholt
90aea51983
Fix translation of saturate value, and wire conditionalmod to 0 for now.
2013-03-04 15:54:21 +00:00
Eric Anholt
b9e6224587
Remove generated source from repo.
2013-03-04 15:54:21 +00:00
