Bspec says JIP and UIP should be the source operands. It is better if
src_operand has a field "reloc_target" according to bspec.
The replicative code in JMPI and branchloop rules can be merged into one.
bspec: BFI1 should not access accumulator. PLN should not use accumulator
as source.
future work in gram.y: show warning if acc is used as dest for
ADDC/SUBB/CMP/CMPN/SHL/BFI1.
fbh: Find the first significant bit searching from the high bits
in src0 and store the result in dst.
fbl: Find the first 1 bit searching from the low bits in src0
and store the result in dst.
The f16to32 instruction converts the half precision float
in src0 to single precision float and storing in dst.
The f32to16 instruction converts the single precision float
in src0 to half precision float and storing in the lower word
of each channel in dst.
Supporting two new operators, bfe and bfi2
bfe: Component-wise extracts a bit field from src2 using the bit field width from src0 and the bit field offset from src1.
bfi2: component-wise performs the bitfield insert operation on src1 and src2 based on the mask in src0.
The shift/reduce conflict mentioned in the comment has been fixed, so
flagreg can return the reg number in the lvalue now. In addition, it will
be easy to add support for flag register f1 on Ivy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.
data_port(
cache_type, /* sampler, render, constant or data(on Ivybridge+) cache */
message_type, /* read or write type */
message_control,
binding_table_index,
write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
header_present)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
since Sandybrdige, there isn't a single function unit for data port read/write.
Instead sampler/render/constant cache unit is introduced, data port read/write
can be specified in a SEND instruction with different cache unit. To keep compatibility,
currently data port read always uses sampler cache unit however data port write
uses render cache unit
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Previously some instructions parsed by this assembler don't follow the
documents.
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu <haofu.han@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
