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Using a dummy reloc that doesn't matter to trick the kernel into synchroizing the rings. v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and switch to MI_COND_BATCH_BUFFER_END as a dummy command on the render ring to avoid PIPE_CONTROL errata. v3: somebody clever decided that in C, you cound from 1, i.e. I915_EXEC_RENDER == 1. It works now ... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>