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https://github.com/tiagovignatti/intel-gpu-tools.git
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tools/range handing: forgot the register map file :(
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Ben Widawsky
parent
62873796c4
commit
d0a7e0ab5a
178
lib/intel_reg_map.c
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178
lib/intel_reg_map.c
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/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include <sys/types.h>
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#include "intel_gpu_tools.h"
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static struct intel_register_range gen_bwcl_register_map[] = {
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{0x00000000, 0x00000fff, INTEL_RANGE_RW},
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{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x00002000, 0x00000fff, INTEL_RANGE_RW},
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{0x00003000, 0x000001ff, INTEL_RANGE_RW},
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{0x00003200, 0x00000dff, INTEL_RANGE_RW},
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{0x00004000, 0x000003ff, INTEL_RANGE_RSVD},
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{0x00004400, 0x00000bff, INTEL_RANGE_RSVD},
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{0x00005000, 0x00000fff, INTEL_RANGE_RW},
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{0x00006000, 0x00000fff, INTEL_RANGE_RW},
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{0x00007000, 0x000003ff, INTEL_RANGE_RW},
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{0x00007400, 0x000014ff, INTEL_RANGE_RW},
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{0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
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{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
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{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
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{0x00010000, 0x00003fff, INTEL_RANGE_RW},
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{0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
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{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
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{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00070000, 0x00002fff, INTEL_RANGE_RW},
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{0x00073000, 0x00000fff, INTEL_RANGE_RW},
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{0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
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{0x00000000, 0x00000000, INTEL_RANGE_END}
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};
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static struct intel_register_range gen4_register_map[] = {
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{0x00000000, 0x00000fff, INTEL_RANGE_RW},
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{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x00002000, 0x00000fff, INTEL_RANGE_RW},
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{0x00003000, 0x000001ff, INTEL_RANGE_RW},
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{0x00003200, 0x00000dff, INTEL_RANGE_RW},
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{0x00004000, 0x000003ff, INTEL_RANGE_RW},
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{0x00004400, 0x00000bff, INTEL_RANGE_RW},
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{0x00005000, 0x00000fff, INTEL_RANGE_RW},
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{0x00006000, 0x00000fff, INTEL_RANGE_RW},
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{0x00007000, 0x000003ff, INTEL_RANGE_RW},
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{0x00007400, 0x000014ff, INTEL_RANGE_RW},
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{0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
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{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
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{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
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{0x00010000, 0x00003fff, INTEL_RANGE_RW},
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{0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
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{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
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{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00070000, 0x00002fff, INTEL_RANGE_RW},
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{0x00073000, 0x00000fff, INTEL_RANGE_RW},
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{0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
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{0x00000000, 0x00000000, INTEL_RANGE_END}
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};
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/* The documentation is a little sketchy on these register ranges. */
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static struct intel_register_range gen6_gt_register_map[] = {
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{0x00000000, 0x00000fff, INTEL_RANGE_RW},
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{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x00002000, 0x00000fff, INTEL_RANGE_RW},
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{0x00003000, 0x000001ff, INTEL_RANGE_RW},
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{0x00003200, 0x00000dff, INTEL_RANGE_RW},
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{0x00004000, 0x00000fff, INTEL_RANGE_RW},
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{0x00005000, 0x0000017f, INTEL_RANGE_RW},
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{0x00005180, 0x00000e7f, INTEL_RANGE_RW},
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{0x00006000, 0x00001fff, INTEL_RANGE_RW},
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{0x00008000, 0x000007ff, INTEL_RANGE_RW},
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{0x00008800, 0x000000ff, INTEL_RANGE_RSVD},
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{0x00008900, 0x000006ff, INTEL_RANGE_RW},
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{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
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{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
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{0x00010000, 0x00001fff, INTEL_RANGE_RW},
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{0x00012000, 0x000003ff, INTEL_RANGE_RW},
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{0x00012400, 0x00000bff, INTEL_RANGE_RW},
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{0x00013000, 0x00000fff, INTEL_RANGE_RW},
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{0x00014000, 0x00000fff, INTEL_RANGE_RW},
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{0x00015000, 0x0000cfff, INTEL_RANGE_RW},
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{0x00022000, 0x00000fff, INTEL_RANGE_RW},
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{0x00023000, 0x00000fff, INTEL_RANGE_RSVD},
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{0x00024000, 0x00000fff, INTEL_RANGE_RW},
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{0x00025000, 0x0000afff, INTEL_RANGE_RSVD},
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{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00040000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00050000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
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{0x00070000, 0x00003fff, INTEL_RANGE_RW},
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{0x00074000, 0x0008bfff, INTEL_RANGE_RSVD},
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{0x00100000, 0x00007fff, INTEL_RANGE_RW},
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{0x00108000, 0x00037fff, INTEL_RANGE_RSVD},
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{0x00140000, 0x0003ffff, INTEL_RANGE_RW},
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{0x00000000, 0x00000000, INTEL_RANGE_END}
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};
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struct intel_register_map
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intel_get_register_map(uint32_t devid)
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{
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struct intel_register_map map;
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if (IS_GEN6(devid)) {
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map.map = gen6_gt_register_map;
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map.top = 0x180000;
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} else if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
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map.map = gen_bwcl_register_map;
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map.top = 0x80000;
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} else if (IS_GEN4(devid) || IS_GEN5(devid)) {
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map.map = gen4_register_map;
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map.top = 0x80000;
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} else {
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fprintf(stderr, "Gen2/3 Ranges are not supported. Please use "
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"unsafe access.");
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abort();
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}
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map.alignment_mask = 0x3;
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return map;
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}
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struct intel_register_range *
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intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode)
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{
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struct intel_register_range *range = map.map;
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uint32_t align = map.alignment_mask;
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if (offset & map.alignment_mask)
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return NULL;
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if (offset >= map.top)
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return NULL;
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while (!(range->flags & INTEL_RANGE_END)) {
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/* list is assumed to be in order */
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if (offset < range->base)
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break;
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if ( (offset >= range->base) &&
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(offset + align) <= (range->base + range->size)) {
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if ((mode & range->flags) == mode)
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return range;
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}
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range++;
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}
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return NULL;
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}
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