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Search for the first Intel dri device.

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This is vital in a multi-GPU system so that we only test the Intel card
and not the discrete GPUs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2011-02-01 13:35:36 +00:00
parent c1e9795050
commit 3c5c8ba71c
8 changed files with 59 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/drmtest.c
View File

@ -29,6 +29,23 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include "drmtest.h"
#include "i915_drm.h"
#include "intel_chipset.h"
static int
is_intel(int fd)
{
struct drm_i915_getparam gp;
int devid;
gp.param = I915_PARAM_CHIPSET_ID;
gp.value = &devid;
if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
return 0;
return IS_INTEL(devid);
}
/** Open the first DRM device we can find, searching up to 16 device nodes */
int drm_open_any(void)
@ -39,8 +56,13 @@ int drm_open_any(void)
for (i = 0; i < 16; i++) {
sprintf(name, "/dev/dri/card%d", i);
fd = open(name, O_RDWR);
if (fd != -1)
if (fd == -1)
continue;
if (is_intel(fd))
return fd;
close(fd);
}
abort();
}
@ -63,6 +85,11 @@ int drm_open_any_master(void)
if (fd == -1)
continue;
if (!is_intel(fd)) {
close(fd);
continue;
}
/* Check that we're the only opener and authed. */
client.idx = 0;
ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client);

2
lib/instdone.c
View File

@ -205,7 +205,7 @@ init_instdone_definitions(uint32_t devid)
gen6_instdone2_bit(GEN6_GS_DONE, "GS");
gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
gen6_instdone2_bit(GEN6_VF_DONE, "VF");
} else if (IS_IRONLAKE(devid)) {
} else if (IS_GEN5(devid)) {
gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");

29
lib/intel_chipset.h
View File

@ -95,7 +95,6 @@
#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
#define IS_IRONLAKE(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
devid == PCI_CHIP_E7221_G || \
@ -111,6 +110,13 @@
devid == PCI_CHIP_Q33_G || \
devid == PCI_CHIP_Q35_G || IS_IGD(devid))
#define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \
devid == PCI_CHIP_845_G || \
devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I865_G)
#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
#define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
devid == PCI_CHIP_I965_Q || \
devid == PCI_CHIP_I965_G_1 || \
@ -120,9 +126,11 @@
IS_G4X(devid))
#define IS_965(devid) (IS_GEN4(devid) || \
IS_IRONLAKE(devid) || \
IS_GEN5(devid) || \
IS_GEN6(devid))
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
#define IS_GEN6(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
@ -131,9 +139,16 @@
devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
devid == PCI_CHIP_SANDYBRIDGE_S)
#define IS_9XX(devid) (IS_915(devid) || \
IS_945(devid) || \
IS_965(devid))
#define HAS_PCH_SPLIT(devid) (IS_IRONLAKE(devid) || \
#define IS_9XX(devid) (IS_GEN3(devid) || \
IS_GEN4(devid) || \
IS_GEN4(devid) || \
IS_GEN6(devid))
#define IS_INTEL(devid) (IS_GEN2(devid) || \
IS_GEN3(devid) || \
IS_GEN4(devid) || \
IS_GEN4(devid) || \
IS_GEN6(devid))
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
IS_GEN6(devid))

2
tools/intel_audio_dump.c
View File

@ -1197,7 +1197,7 @@ int main(int argc, char **argv)
if (HAS_PCH_SPLIT(devid) || getenv("HAS_PCH_SPLIT")) {
intel_check_pch();
dump_cpt();
} else if (IS_IRONLAKE(devid))
} else if (IS_GEN5(devid))
dump_ironlake();
else
dump_eaglelake();

8
tools/intel_decode.c
View File

@ -1644,7 +1644,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
case 0x6101:
if (IS_GEN6(devid))
sba_len = 10;
else if (IS_IRONLAKE(devid))
else if (IS_GEN5(devid))
sba_len = 8;
else
sba_len = 6;
@ -1663,14 +1663,14 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
if (IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "dynamic");
state_base_out(data, hw_offset, i++, "indirect");
if (IS_IRONLAKE(devid) || IS_GEN6(devid))
if (IS_GEN5(devid) || IS_GEN6(devid))
state_base_out(data, hw_offset, i++, "instruction");
state_max_out(data, hw_offset, i++, "general");
if (IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "dynamic");
state_max_out(data, hw_offset, i++, "indirect");
if (IS_IRONLAKE(devid) || IS_GEN6(devid))
if (IS_GEN5(devid) || IS_GEN6(devid))
state_max_out(data, hw_offset, i++, "instruction");
return len;
@ -2071,7 +2071,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int
instr_out(data, hw_offset, 0,
"3DSTATE_DEPTH_BUFFER\n");
if (IS_IRONLAKE(devid) || IS_GEN6(devid))
if (IS_GEN5(devid) || IS_GEN6(devid))
instr_out(data, hw_offset, 1, "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
get_965_surfacetype(data[1] >> 29),
get_965_depthformat((data[1] >> 18) & 0x7),

2
tools/intel_disable_clock_gating.c
View File

@ -40,7 +40,7 @@ int main(int argc, char** argv)
pci_dev = intel_get_pci_device();
intel_get_mmio(pci_dev);
if (IS_IRONLAKE(pci_dev->device_id)) {
if (IS_GEN5(pci_dev->device_id)) {
printf("Restore method:\n");
printf("intel_reg_write 0x%x 0x%08x\n",

2
tools/intel_gpu_top.c
View File

@ -409,7 +409,7 @@ int main(int argc, char **argv)
}
ring_init(&render_ring);
if (IS_GEN4(devid) || IS_IRONLAKE(devid))
if (IS_GEN4(devid) || IS_GEN5(devid))
ring_init(&bsd_ring);
if (IS_GEN6(devid)) {
ring_init(&bsd6_ring);

2
tools/intel_gtt.c
View File

@ -56,7 +56,7 @@ int main(int argc, char **argv)
exit(1);
}
if (IS_G4X(devid) || IS_IRONLAKE(devid))
if (IS_G4X(devid) || IS_GEN5(devid))
gtt = ((unsigned char *)mmio + MB(2));
else if (IS_965(devid))
gtt = ((unsigned char *)mmio + KB(512));