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12 Commits

Author SHA1 Message Date
Thomas Wood d4e3b6a0f5 lib: various documentation fixes 
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
 2014-10-17 15:34:43 +01:00
Xiang, Haihao fe4e4c176c rendercopy/skl: Set the URB VS start address to 4 
A value less than 4 might result in GPU hang on simulation

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui 5b46cd335d rendercopy/skl: Follow the spec to add the Pipeline selection mask 
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui 8e62f78999 rendercopy/skl: Emit 3DSTATE_WM_HZ_OP 
This is from that on BDW. Without it, the pixel pipeline can't work well.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui 833e476624 rendercopy/skl: Fix the 3DSTATE_DS instruction length 
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui 7628268952 rendercopy/skl: Fix the STATE_BASE_ADDRESS instruction length 
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui 77a9ed7da2 rendercopy/skl: Set Instruction Buffer size Modify Enable to 1 
This is ported from that on BDW.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui e539e91cf5 rendercopy/skl: update instruction length 
This is ported from that on BDW.

v2: Only bump the prefix when we need to program the instruction
differently with the previous generations.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui f04bf00c0d rendercopy/skl: Pass the context to rendercopy function on SKL 
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
 2014-09-30 12:21:02 +01:00
Damien Lespiau ecd659e000 rendercopy/skl: Update 3DSTATE_SBE 
SBE has now to be explicitely told which channels of which components
are used by the pixel shader.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
 2014-09-30 12:21:02 +01:00
Damien Lespiau e5b850cb34 rendercopy/skl: Set the 3DSTATE_VF state 
This is to ensure the "Component Packing Enable" bit is set to 0.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
 2014-09-30 12:21:02 +01:00
Damien Lespiau aa7f9cf881 rendercopy/skl: Start the gen9 rendercopy from the gen8 version 
v2 (Ben): Rebased on:
 commit ea11d103e0
Author: Oscar Mateo <oscar.mateo@intel.com>
Date:   Tue Nov 12 11:50:35 2013 +0000

    build: list all test/tool/lib source files in their own Makefile.sources

v3: (Ben): Rebased on the doc/API rework. Probably needs review

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
 2014-09-30 12:21:02 +01:00