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rendercopy/skl: Emit 3DSTATE_WM_HZ_OP
This is from that on BDW. Without it, the pixel pipeline can't work well. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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@ -715,8 +715,19 @@ gen9_emit_ds(struct intel_batchbuffer *batch) {
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OUT_BATCH(0);
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}
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static void
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gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) {
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OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen8_emit_null_state(struct intel_batchbuffer *batch) {
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gen8_emit_wm_hz_op(batch);
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gen8_emit_hs(batch);
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OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
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OUT_BATCH(0);
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