Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.
v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.
v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Also start to shortly explain testcases with an easily-greppable
header like this:
/*
* Testcase:
*
* [Possible further explanation.]
*
*/
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
MI_*/PIPE_CONTROL writes need to be in DOMAIN_INSTRUCTION, because
that is what mesa uses and I plan to use this to work around a
gen6 ppgtt issue.
Also testing with intentionally b0rked GFX_MODE on my snb shows that
we need to increase the loop counter a bit to reliably hit the tlb
invalidation problem. Test still completes within a few seconds.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Previously, "make check" failed because the main() function was not
defined.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Add a couple of simple store dword tests to test memory coherence.
gem_storedw_loop simply executes a batch that continually stores an
incremented value to a target buffer object, checking the results after
each batch completes.
gem_storedw_batches_loop does the same thing, but creates a new command
batch buffer for each iteration, which can exercise the buffer creation
code. This test is based on one from Andrzej Kacprowski from Intel.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
In other news: We've been missing a unmapping_mapping_range somewhere
in the kernel. But lazy me never came around to digging up the real
cause.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
As signals cause the syscalls to be interrupted, we often need to clean
up partial state before returning to userspace. Often a source of
unamusing bugs, so encourage gem_stress to provoke them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
gem_stress -p1 is much more evil than gem_stress -c1, it also manages
to tear appart untiled workloads!
Now duct-taping over it still works (--apply-duct-tape) ... hm.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
When using testdisplay on GM965 and Pineview with LVDS, it will fail to
set a mode because the first unused crtc can't be used for LVDS. So
check the possible_crtcs to make sure the crtc can be used.
Signed-off-by: Hai Lan <hai.lan@intel.com>
Remember the 3D pipeline is much more restricted than the BLT engine,
and we were feeding it buffers much larger than either the
render engine or the sampler could manager.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Gah, in my excitement of reproducing the failure reported by
gem_stress, I missed using fenced relocs for the BLT.
Fortunately, it doesn't affect the presence of the error.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
... and we have a winner: gen3_mixed_blits reproduces the issue Daniel
Vetter originally found. It seems clear that we have some incoherence
between the RENDER and BLT units on gen3 that no amount of MI_FLUSH can
hide. Hmmm....
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
gem_stress is unhappy with tiled render copies on gen3. This is a simple
little test to ensure that a set of pure copies with a working set
larger than the aperture are handled correctly.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
