flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2026-08-11 16:32:58 +00:00
Code Issues Releases Wiki Activity
1,093 Commits 13 Branches 0 Tags
8ca55688ea01a688677996570fb1f6626469d99d
Commit Graph

157 Commits

Author SHA1 Message Date
Homer Hsing 8ca55688ea Supporting bit field extract and bit field insert 2 
Supporting two new operators, bfe and bfi2
bfe: Component-wise extracts a bit field from src2 using the bit field width from src0 and the bit field offset from src1.
bfi2: component-wise performs the bitfield insert operation on src1 and src2 based on the mask in src0.
 2013-03-04 15:54:31 +00:00
Homer Hsing 210510cebb Supporting LRP: dest = src0 * src1 + (1-src0) * src2 2013-03-04 15:54:31 +00:00
Homer Hsing a034bcbd04 Support trinary source instruction "multiply add". 
MAD (Multiply ADd) computes dst <- src1*src2 + src0.

Tried best to follow previous variable naming habit.

Also renamed "triinstruction" -> "trinaryinstruction" in grammar parser
for better readability.
 2013-03-04 15:54:31 +00:00
Homer Hsing 0d3f8495ea add data structure in src/brw_structs.h for supporting three-source-operator instruncions 2013-03-04 15:54:30 +00:00
Homer Hsing 75f1d80982 Comment magic words "da1", "da16", "ia1", and "ia16" 2013-03-04 15:54:30 +00:00
Homer Hsing aab7cd5cc5 close File yyin before calling yylex_destroy 
This patch makes sure file handler yyin is closed.
yylex_destroy() calls yy_init_globals(), which reset yyin to 0.
Therefore if we do not close yyin before yylex_destroy(), yyin
will not be closed anymore.
 2013-03-04 15:54:30 +00:00
Homer Hsing 31401afe78 Call yylex_destroy() to free memory after yyparse() 2013-03-04 15:54:30 +00:00
Homer Hsing 302ca73198 Close input file handler yyin after yyparse 2013-03-04 15:54:30 +00:00
Homer Hsing f282ea689b Fix a typo ... lable -> label 2013-03-04 15:54:30 +00:00
Lu Guanqun ea1fcf0b44 fix the label checking logics 
Signed-off-by: Lu Guanqun <guanqun.lu@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao 4d75db550e Waring if both predication and conditional modifier are enabled but use different flag registers 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao 3ffbe96c1e Add support for flag register f1 on Ivy bridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao 2f772dd67b s/flag_reg_nr/flag_subreg_nr for an instruction 
s/flagreg/flag_subreg_nr for a condition

They are flag subregister number indeed

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao 968d2d7ef6 Remove flag_reg_nr from the DW3 of an instruction 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao f3f6ba24e6 Change the rule for flag register 
The shift/reduce conflict mentioned in the comment has been fixed, so
flagreg can return the reg number in the lvalue now. In addition, it will
be easy to add support for flag register f1 on Ivy bridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao 128053f120 Accept symbol register as the leading register of the request 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Ben Widawsky fc2995b59a disasm: decode SENDC like SEND 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:29 +00:00
Ben Widawsky 35c217b986 disasm: add gen6 style send decoding 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:29 +00:00
Ben Widawsky 22505dc051 disasm: add sendc 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:29 +00:00
Ben Widawsky 26c36abdf6 disasm: add pln instruction 
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 0b5f7fa049 A new syntax of SEND intruction on Ivybridge 
[(<pred>)] send (<exec_size>) reg greg imm6 reg32a

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao d6bc0e4ea3 bump version to 1.2 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 86f8ca6af9 Support VME on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 27050395d2 Support DP for sampler/render/constant/data cache 
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao e97f0bca5f sampler/render/constant cache unit since Sandybridge 
since Sandybrdige, there isn't a single function unit for data port read/write.
Instead sampler/render/constant cache unit is introduced, data port read/write
can be specified in a SEND instruction with different cache unit. To keep compatibility,
currently data port read always uses sampler cache unit however data port write
uses render cache unit

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 6a3a9e7148 fix an error in commit cf76278 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 46ffdd5df7 SEND uses GRFs instead of MRFs on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 67d4ed665d Add support for sample (00000) on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao c8d6bf353e Add support for data port read/write on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao 6fa6b45daf Add -g 7 for Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Feng, Boqun 37d68103a8 Send instruction on PRE-ILK 
[(<pred>)] send (<exec_size>) <pdst> <cdst> <src0> <desc>
 2013-03-04 15:54:28 +00:00
Zhou Chang 52399867bf Add VME support in SEND 2013-03-04 15:54:28 +00:00
Ben Widawsky 83a5c38e12 intel-gen4asm: add byte array style disasm 
I previously added a byte array style output for intel-gen4asm, but
there was no way to disassemble here. Well here that is.
 2013-03-04 15:54:28 +00:00
Ben Widawsky cbfab5f415 intel-gen4asm: have a C-like binary output 
Have the assembler support a byte array output. This is useful for
writing blobs which can directly be linked code that wishes to upload to
the EU.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao e7f4dc6e39 fix the parameters of register region 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao 85da7b9e8a send instruction on GEN6 
[(<pred>)] send (<exec_size>) reg mreg imm6 imm32

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao 852216d6e3 fix notification count register 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao 27b4303a30 Support instructions which strictly follow the documents. 
Previously some instructions parsed by this assembler don't follow the
documents.

Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Chen, Yangyang 66649d7b4e 1. fix DOT 
2. rule for instrseq

Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
 2013-03-04 15:54:28 +00:00
Chen, Yangyang bf06f07d5b fix CHANNEL select 
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao 14c0bd0fb3 Support for headerless write 
Add a new parameter to write

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao d0ae329708 bump version to 1.1 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao 5405532ffc add support for math instruction on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao f1f5208e1e add support for plane instruction (pln) 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao dcdde5347e Send on Sandybridge uses a message register as operand src0 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao c2382cab55 no compression flag on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao 718cd6cb42 print error message when using math function on Sandybridge. 
Sandybridge doesn't have math funtion, instead it supports a set of math
instructions. The support for math instructions will be added later.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao 9d2be25838 sampler, urb write, null and gateway on Sandybridge are same as Ironlake. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao a8458d5d5e add support for data port read on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao 61784dbc97 add support for data port write on Sandybridge. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00