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27 Commits

Author SHA1 Message Date
Homer Hsing
751838e809 Add second_reloc_target in the data structure. 
Since Gen6+, some branching instructions have two relocation targets.
 2013-03-04 15:54:33 +00:00
Homer Hsing
741008e050 Fix field length of JIP for one-offset-branch in Gen6 
Such JIP has 25 bits length in Gen6.
 2013-03-04 15:54:33 +00:00
Homer Hsing
c3bcc7dbeb Rename brw_instruction.bits3.if_else to branch 
Because that field will be used for all branch instructions
 2013-03-04 15:54:32 +00:00
Homer Hsing
375d1fd7b2 Renaming according to BSPEC: jump_count -> JIP; pop_count -> UIP. 
Since bspec SNB+, jump_count and pop_count is renamed to JIP and uIP.
 2013-03-04 15:54:32 +00:00
Homer Hsing
0d3f8495ea add data structure in src/brw_structs.h for supporting three-source-operator instruncions 2013-03-04 15:54:30 +00:00
Homer Hsing
75f1d80982 Comment magic words "da1", "da16", "ia1", and "ia16" 2013-03-04 15:54:30 +00:00
Xiang, Haihao
3ffbe96c1e Add support for flag register f1 on Ivy bridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
2f772dd67b s/flag_reg_nr/flag_subreg_nr for an instruction 
s/flagreg/flag_subreg_nr for a condition

They are flag subregister number indeed

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
968d2d7ef6 Remove flag_reg_nr from the DW3 of an instruction 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:30 +00:00
Xiang, Haihao
27050395d2 Support DP for sampler/render/constant/data cache 
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
67d4ed665d Add support for sample (00000) on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
c8d6bf353e Add support for data port read/write on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Zhou Chang
52399867bf Add VME support in SEND 2013-03-04 15:54:28 +00:00
Xiang, Haihao
27b4303a30 Support instructions which strictly follow the documents. 
Previously some instructions parsed by this assembler don't follow the
documents.

Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
a8458d5d5e add support for data port read on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
61784dbc97 add support for data port write on Sandybridge. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
4f777e73f1 fix send instruction on Sandybridge 
Send doesn't have implied move on Sandybridge, the SFID moves to bits[24,27] which
is used as the destination of the implied move on Prev GEN6.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
55d81c4ce7 add AccWrCtrl flag on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
5bcf1f5a03 always set destination horiz stride for Align16 to 1 on Sandybridge. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
5261b8475e change read message format on GEN5 
to re-use a lot of shaders for GEN5.
 2013-03-04 15:54:26 +00:00
Xiang Haihao
549b751afb Add support for GEN5 
Add a new option [-g n], n=4(GEN4),5(GEN5). If don't use -g,
the default value is 4(GEN4)
 2013-03-04 15:54:26 +00:00
Zou Nanhai
be9bcee15f Add support for labeled and conditional branches 
Signed-off-by: Keith Packard <keithp@keithp.com>
 2013-03-04 15:54:26 +00:00
Keith Packard
5a2ec836e1 Support more addressing modes in disasm 2013-03-04 15:54:26 +00:00
Zou Nan hai
26afe90126 Add thread_spawner message target support. 2013-03-04 15:54:26 +00:00
Keith Packard
2033aea3dd Add conditional support to assembler. Add align16 dest support to disasm. 
This is working towards round-tripping mesa programs. Still need indirect
register addressing and align16 source support.
 2013-03-04 15:54:26 +00:00
Eric Anholt
78cb82a1e2 Add some masks in comments that will help with writing tests. 2013-03-04 15:54:24 +00:00
Eric Anholt
9b40c3724a Add autotools build system, and rearrange directory layout. 2013-03-04 15:54:23 +00:00