flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-09 17:06:14 +00:00
Code Issues Releases Wiki Activity

Fix field length of JIP for one-offset-branch in Gen6

Browse Source 
Such JIP has 25 bits length in Gen6.
This commit is contained in:
Homer Hsing 2012-09-20 13:09:15 +08:00 committed by Damien Lespiau
parent 6983eebf47
commit 741008e050
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
assembler/src/brw_structs.h
View File

@ -1311,7 +1311,10 @@ struct brw_instruction
{
GLint JIP:16; /* bspec: both the JIP and UIP are signed 16-bit numbers */
GLint UIP:16;
} branch; /* for branch instructions: brc, brd, if, else, endif, while, break, cont, call, ret, halt, ... */
} branch_2_offset; /* for Gen6, Gen7 2-offsets branch instructions */
GLint JIP; /* for Gen6, Gen7 1-offset branch instructions
Gen6 uses low 25 bits. Gen7 uses low 16 bits. */
struct {
GLuint function:4;

6
assembler/src/main.c
View File

@ -351,12 +351,12 @@ int main(int argc, char **argv)
entry1->inst_offset - entry->inst_offset;
int delta = (entry->instruction.header.opcode == BRW_OPCODE_JMPI ? 1 : 0);
if (gen_level >= 5)
entry->instruction.bits3.branch.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
entry->instruction.bits3.JIP = 2 * (offset - delta); // bspec: the jump distance in number of eight-byte units
else
entry->instruction.bits3.branch.JIP = offset - delta;
entry->instruction.bits3.JIP = offset - delta;
if (entry->instruction.header.opcode == BRW_OPCODE_ELSE)
entry->instruction.bits3.branch.UIP = 1;
entry->instruction.bits3.branch_2_offset.UIP = 1;
found = 1;
break;
}