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335 Commits

Author SHA1 Message Date
Xiang, Haihao
86f8ca6af9 Support VME on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
27050395d2 Support DP for sampler/render/constant/data cache 
Since Sandybridge, DP supports cache select for read/write. Some write messages such as
OWord Block Write don't support render cache any more on Ivybridge. So introduce a
generic data_port messsage for Sandybridge+.

    data_port(
        cache_type,   /* sampler, render, constant or data(on Ivybridge+) cache */
        message_type, /* read or write type */
        message_control,
        binding_table_index,
        write_commit_or_category, /* write commit on Sandybridge, category on Ivybridge+ */
        header_present)

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
e97f0bca5f sampler/render/constant cache unit since Sandybridge 
since Sandybrdige, there isn't a single function unit for data port read/write.
Instead sampler/render/constant cache unit is introduced, data port read/write
can be specified in a SEND instruction with different cache unit. To keep compatibility,
currently data port read always uses sampler cache unit however data port write
uses render cache unit

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
6a3a9e7148 fix an error in commit cf76278 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
46ffdd5df7 SEND uses GRFs instead of MRFs on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
67d4ed665d Add support for sample (00000) on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
c8d6bf353e Add support for data port read/write on Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Xiang, Haihao
6fa6b45daf Add -g 7 for Ivybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:29 +00:00
Feng, Boqun
37d68103a8 Send instruction on PRE-ILK 
[(<pred>)] send (<exec_size>) <pdst> <cdst> <src0> <desc>
 2013-03-04 15:54:28 +00:00
Zhou Chang
52399867bf Add VME support in SEND 2013-03-04 15:54:28 +00:00
Ben Widawsky
83a5c38e12 intel-gen4asm: add byte array style disasm 
I previously added a byte array style output for intel-gen4asm, but
there was no way to disassemble here. Well here that is.
 2013-03-04 15:54:28 +00:00
Ben Widawsky
cbfab5f415 intel-gen4asm: have a C-like binary output 
Have the assembler support a byte array output. This is useful for
writing blobs which can directly be linked code that wishes to upload to
the EU.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
e7f4dc6e39 fix the parameters of register region 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
85da7b9e8a send instruction on GEN6 
[(<pred>)] send (<exec_size>) reg mreg imm6 imm32

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
852216d6e3 fix notification count register 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
27b4303a30 Support instructions which strictly follow the documents. 
Previously some instructions parsed by this assembler don't follow the
documents.

Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Chen, Yangyang
66649d7b4e 1. fix DOT 
2. rule for instrseq

Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
 2013-03-04 15:54:28 +00:00
Chen, Yangyang
bf06f07d5b fix CHANNEL select 
Signed-off-by: Chen, Yangyang <yangyang.chen@intel.com>
Signed-off-by: Han, Haofu     <haofu.han@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
14c0bd0fb3 Support for headerless write 
Add a new parameter to write

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
d0ae329708 bump version to 1.1 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
5405532ffc add support for math instruction on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
f1f5208e1e add support for plane instruction (pln) 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:28 +00:00
Xiang, Haihao
dcdde5347e Send on Sandybridge uses a message register as operand src0 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
c2382cab55 no compression flag on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
718cd6cb42 print error message when using math function on Sandybridge. 
Sandybridge doesn't have math funtion, instead it supports a set of math
instructions. The support for math instructions will be added later.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
9d2be25838 sampler, urb write, null and gateway on Sandybridge are same as Ironlake. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
a8458d5d5e add support for data port read on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
61784dbc97 add support for data port write on Sandybridge. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
4f777e73f1 fix send instruction on Sandybridge 
Send doesn't have implied move on Sandybridge, the SFID moves to bits[24,27] which
is used as the destination of the implied move on Prev GEN6.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
55d81c4ce7 add AccWrCtrl flag on Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
5bcf1f5a03 always set destination horiz stride for Align16 to 1 on Sandybridge. 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
95d0ce48f6 fix jump count for Sandybridge. 
It is same as Ironlake.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Xiang, Haihao
eb92c228cd add -g 6 for Sandybridge 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:27 +00:00
Zou Nan hai
db8aedc745 use left recursion instead of right recursion to avoid memory exhausted issue when compiling large source files 2013-03-04 15:54:27 +00:00
Eric Anholt
dea75a6935 Fix setup of immediate types for gen4 disasm. 
Caught by clang.
 2013-03-04 15:54:27 +00:00
Eric Anholt
a6f1455019 disasm: Print out ELSE and ENDIF src1 arguments like IF does. 2013-03-04 15:54:27 +00:00
Eric Anholt
459c95b20c whitespace cleanup from Mesa import. 2013-03-04 15:54:26 +00:00
Zou Nan hai
c6f2da4e82 1. type syntax :ud :uw etc 
2. empty instruction option
3. remove a conflict
 2013-03-04 15:54:26 +00:00
Zou Nan hai
5608d2765d support simple expression 2013-03-04 15:54:26 +00:00
Xiang, Haihao
8521146207 add intel-gen4asm.pc.in 
bump version to 1.0
 2013-03-04 15:54:26 +00:00
Xiang, Haihao
60cf6e09dd the offset of JMPI is in unit of 64bits on GEN5. 
This fix is only applied for JMPI label. It is up to you
to use a right offset for JMPI imm32|reg in your program.
 2013-03-04 15:54:26 +00:00
Xiang, Haihao
5261b8475e change read message format on GEN5 
to re-use a lot of shaders for GEN5.
 2013-03-04 15:54:26 +00:00
Xiang Haihao
549b751afb Add support for GEN5 
Add a new option [-g n], n=4(GEN4),5(GEN5). If don't use -g,
the default value is 4(GEN4)
 2013-03-04 15:54:26 +00:00
Zou Nanhai
be9bcee15f Add support for labeled and conditional branches 
Signed-off-by: Keith Packard <keithp@keithp.com>
 2013-03-04 15:54:26 +00:00
Keith Packard
5a2ec836e1 Support more addressing modes in disasm 2013-03-04 15:54:26 +00:00
Eric Anholt
d866fff116 Fix compiler warning from missing include. 2013-03-04 15:54:26 +00:00
Zou Nan hai
807f8768e9 Add support for dp_read message. 2013-03-04 15:54:26 +00:00
Zou Nan hai
26afe90126 Add thread_spawner message target support. 2013-03-04 15:54:26 +00:00
Keith Packard
2033aea3dd Add conditional support to assembler. Add align16 dest support to disasm. 
This is working towards round-tripping mesa programs. Still need indirect
register addressing and align16 source support.
 2013-03-04 15:54:26 +00:00
Keith Packard
d8057c9bcd Add math and urb units, deal with nop 2013-03-04 15:54:26 +00:00