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https://github.com/tiagovignatti/intel-gpu-tools.git
synced 2025-06-10 09:26:10 +00:00
support simple expression
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8521146207
commit
5608d2765d
@ -80,8 +80,9 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
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%token LCURLY RCURLY
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%token LSQUARE RSQUARE
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%token COMMA
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%token DOT
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%token PLUS MINUS ABS
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%token DOT ABS
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%left PLUS MINUS
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%left MULTIPLY DIVIDE
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%token <integer> TYPE_UD TYPE_D TYPE_UW TYPE_W TYPE_UB TYPE_B
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%token <integer> TYPE_VF TYPE_HF TYPE_V TYPE_F
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@ -120,6 +121,7 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
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%token <integer> X Y Z W
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%type <integer> exp
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%type <instruction> instruction unaryinstruction binaryinstruction
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%type <instruction> binaryaccinstruction triinstruction sendinstruction
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%type <instruction> jumpinstruction branchloopinstruction elseinstruction
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@ -152,7 +154,15 @@ void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg,
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%type <src_operand> indirectsrcoperand
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%type <src_operand> src srcimm imm32reg payload srcacc srcaccimm swizzle
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%type <src_operand> relativelocation relativelocation2 locationstackcontrol
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%%
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exp: INTEGER { $$ = $1; }
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| exp MULTIPLY exp { $$ = $1 * $3; }
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| exp DIVIDE exp { if ($3) $$ = $1 / $3; else YYERROR;}
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| exp PLUS exp { $$ = $1 + $3; }
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| exp MINUS exp { $$ = $1 - $3; }
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| MINUS exp { $$ = -$2;}
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| LPAREN exp RPAREN { $$ = $2; }
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ROOT: instrseq
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{
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@ -287,8 +297,8 @@ binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN
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triinstruction: sendinstruction
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;
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sendinstruction: predicate SEND execsize INTEGER post_dst payload msgtarget
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MSGLEN INTEGER RETURNLEN INTEGER instoptions
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sendinstruction: predicate SEND execsize exp post_dst payload msgtarget
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MSGLEN exp RETURNLEN exp instoptions
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{
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/* Send instructions are messy. The first argument is the
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* post destination -- the grf register that the response
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@ -1030,12 +1040,12 @@ addrparam: addrreg immaddroffset
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* from the address register in register-indirect register access.
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*/
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immaddroffset: /* empty */ { $$ = 0; }
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| INTEGER
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| exp
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;
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/* 1.4.5: Register files and register numbers */
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subregnum: DOT INTEGER
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subregnum: DOT exp
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{
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$$ = $2;
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}
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@ -1324,7 +1334,7 @@ locationstackcontrol:
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;
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/* 1.4.7: Regions */
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dstregion: LANGLE INTEGER RANGLE
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dstregion: LANGLE exp RANGLE
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{
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/* Returns a value for a horiz_stride field of an
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* instruction.
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@ -1336,7 +1346,7 @@ dstregion: LANGLE INTEGER RANGLE
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}
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;
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region: LANGLE INTEGER COMMA INTEGER COMMA INTEGER RANGLE
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region: LANGLE exp COMMA exp COMMA exp RANGLE
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{
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memset (&$$, '\0', sizeof ($$));
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$$.vert_stride = ffs($2);
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@ -1349,7 +1359,7 @@ region: LANGLE INTEGER COMMA INTEGER COMMA INTEGER RANGLE
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* a vertical stride, you use subsequent address registers to get a new base
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* offset for the next row.
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*/
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region_wh: LANGLE INTEGER COMMA INTEGER RANGLE
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region_wh: LANGLE exp COMMA exp RANGLE
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{
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memset (&$$, '\0', sizeof ($$));
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$$.vert_stride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
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@ -1450,8 +1460,8 @@ writemask_w: /* empty */ { $$ = 0; }
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;
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/* 1.4.11: Immediate values */
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imm32: INTEGER { $$.r = imm32_d; $$.u.d = $1; }
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| MINUS INTEGER { $$.r = imm32_d; $$.u.d = -$2; }
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imm32: exp { $$.r = imm32_d; $$.u.d = $1; }
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| MINUS exp { $$.r = imm32_d; $$.u.d = -$2; }
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| NUMBER { $$.r = imm32_f; $$.u.f = $1; }
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;
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@ -1504,7 +1514,7 @@ abs: /* empty */ { $$ = 0; }
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| ABS { $$ = 1; }
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;
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execsize: LPAREN INTEGER RPAREN
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execsize: LPAREN exp RPAREN
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{
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/* Returns a value for the execution_size field of an
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* instruction.
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@ -113,7 +113,6 @@ extern char *input_filename;
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"transpose" { return TRANSPOSE; }
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"interleave" { return INTERLEAVE; }
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":" { return COLON; }
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";" { return SEMICOLON; }
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"(" { return LPAREN; }
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")" { return RPAREN; }
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@ -127,6 +126,9 @@ extern char *input_filename;
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"." { return DOT; }
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"+" { return PLUS; }
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"-" { return MINUS; }
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"*" { return MULTIPLY;}
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"/" { return DIVIDE; }
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":" { return COLON; }
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"(abs)" { return ABS; }
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/* Most register accesses are lexed as REGFILE[0-9]+, to prevent the register
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