The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate
for the extended message descriptors. And some bits of SEND instruction are defined
as the extdesc field.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
READ(...) is used for Render Target read and Media Block read. But there is no
sampler cache agent on gen9. At the same time two message types don't
share the same cache agent any more. So a parameter is needed for cache agent.
The 2th parameter of read(...) is not used for gen6/gen7/gen8. Hence it is
reused as cache agent for SKL as that on ILK.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The Sampler/Constant cache is read-only. And it can't be used as
the target cache agent of WRITE message.
Reviewed-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
write(...) is used for Render Target Write and Media Block Write.
The two message types no longer share the same cache agent on GEN8,
So a parameter is needed for cache agent. The 4th parameter of write()
is used for write commit bit which has been removed since GEN7. Hence
we can re-use the 4th parameter as cache agent on GEN8
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This is required to send some messages to data port in GPU shader.
For example: media_block_write message.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This was originally part of:
commit 62298329350b965e4bbfc558e5a4b1b3646742ea
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Aug 14 14:21:16 2013 -0700
assembler: error for the wrong syntax of SEND instruction on GEN6+
I merged that patch separately, but this tiny hunk was leftover. In
order to not muck in changing too much history, I am leaving this as a
discrete patch, but with the changed commit message
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Still some work needed there, but enough for rendercopy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This allows to use the same functions to validate operands on gen8 for
now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
We should now support alu2 intructions with direct register addressing.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' assembler/*.[ch]
Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.
Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This allow us to factor out the test that checks if, when using both
predicates and conditional modifiers, we are using the same flag
register.
Also get rid of of a FIXME that we are now dealing with (the warning
mentioned above).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Like with the predicate fields before, there's no need to use the full
instruction to collect the list of options. This allows us to decouple
the list of options from a specific instruction encoding.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Right now we have duplicated code for when the option is the last in the
list or not. Put that code in a common function.
Interestingly it appears that both sides haven't been kept in sync and
that EOT and ACCWRCTRL had limitations on where they had to be in the
option list. It's fixed now!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Rather than user a full instruction for that. Also use
set_instruction_predicate() for a case that coud not be done like that
before the refactoring (because everyone now uses the same instruction
structure).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Now that all instructions (relocatable or not) are struct
brw_program_instructions, this means we can move the relocation specific
information out the "relocatable instruction" structure. This will allow
us to share the relocation information between different types of
instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This will be less typing for the refactoring to come (which is use
struct brw_program_instruction in gram.y for the type of all the
instructions).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Everything is now aligned to be able to use brw_set_src1() in the
opcode generation, so use it.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This way we ensure to have a single place where these are handled. The
immediate benefit is that now line numbers are always printed out, which
is quite handy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().
To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.
We can fix all this, but it requires validation, something that I cannot
do right now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Another check (that we hit if we try to use brw_set_src0()). Again,
protect it with the -W option.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The list of region restrictions in bspec do say that we can't have:
width == 1 && hstrize != 0
We do have plenty of assembly code that don't respect that behaviour. So
let's hide the warning under a -W flag (for now) while we fix things.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Now that we have locations, we can write error() and warn() functions
giving more information about where it's going wrong.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Let's generate location information about the tokens we are parsing.
This can be used to give accurate location when reporting errors and
warnings.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
