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	assembler/bdw: SEND instruction
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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				@ -1274,7 +1274,6 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
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		  memset(&$$, 0, sizeof($$));
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		  set_instruction_opcode(&$$, $2);
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                  GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
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		  set_instruction_predicate(&$$, &$1);
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		  $4.width = $3;
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@ -1297,7 +1296,13 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
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                  set_instruction_src0(&$$, &src0, NULL);
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		  set_instruction_src1(&$$, &$7, NULL);
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                  GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
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                  if (IS_GENp(8)) {
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                      gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
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                      gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
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		  } else {
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                      GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
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                      GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
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                  }
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		}
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		| predicate sendop execsize dst sendleadreg sndopr directsrcoperand instoptions
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		{
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@ -1315,7 +1320,6 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
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		  memset(&$$, 0, sizeof($$));
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		  set_instruction_opcode(&$$, $2);
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                  GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
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		  set_instruction_predicate(&$$, &$1);
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		  $4.width = $3;
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@ -1338,7 +1342,14 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
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                  set_instruction_src0(&$$, &src0, NULL);
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                  set_instruction_src1(&$$, &$7, &@7);
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                  GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
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                  if (IS_GENp(8)) {
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                      gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
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                      gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
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		  } else {
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                      GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
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                      GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
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                  }
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		}
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		| predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions
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		{
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