flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-10 17:36:11 +00:00
Code Issues Releases Wiki Activity

assembler: switch the order of swizzle and regtype to match the BNF of the assembly

Browse Source 
Fortunately our existing source didn't use swizzle.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631
Tested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This commit is contained in:
Xiang, Haihao 2014-03-25 13:41:25 +08:00 committed by Damien Lespiau
parent a6eaa29271
commit 881afff297
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
assembler/gram.y
View File

@ -2262,21 +2262,21 @@ directsrcoperand: negate abs symbol_reg region regtype
$$.reg.type = $3.type;
}
}
| negate abs directgenreg region regtype swizzle
| negate abs directgenreg region swizzle regtype
{
memset (&$$, '\0', sizeof ($$));
$$.reg.address_mode = BRW_ADDRESS_DIRECT;
$$.reg.file = $3.file;
$$.reg.nr = $3.nr;
$$.reg.subnr = $3.subnr;
$$.reg.type = $5.type;
$$.reg.type = $6.type;
$$.reg.vstride = $4.vert_stride;
$$.reg.width = $4.width;
$$.reg.hstride = $4.horiz_stride;
$$.default_region = $4.is_default;
$$.reg.negate = $1;
$$.reg.abs = $2;
$$.reg.dw1.bits.swizzle = $6.reg.dw1.bits.swizzle;
$$.reg.dw1.bits.swizzle = $5.reg.dw1.bits.swizzle;
}
| srcarchoperandex
;