Still some work needed there, but enough for rendercopy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This allows to use the same functions to validate operands on gen8 for
now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
We should now support alu2 intructions with direct register addressing.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
It's not hitting a valid assertion that it tries to write an instruction
without a defined execution size (because the "default" exec_size never
end up being set).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Same as:
commit 497814f2f2
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Tue Aug 20 14:52:05 2013 +0100
assembler: Revert "Automatically run all test cases."
make check will define srcdir and buildir variables for us.
This reverts commit 1c009349bc.
The tests where supposed to be run through make check, not running the
"run-test.sh" standalone. So revert that patch to have make check work
as intended.
This reverts commit 6983eebf47.
So when making changes in code using that function, we get warnings
about mismatches between the format string and arguments.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
dest_horizontal_stride needs go through the horiz_stride[] indirection
to pick up the rigth stride when its value is 11b (4 elements).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' assembler/*.[ch]
Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.
Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
I originally moved struct opcode_desc from brw_context.h to brw_eu.h on
the mesa side, but that was before the realization we needed struct
brw_context if we wanted to not touch the code too much.
So put it back there now that the mesa patch has been dropped.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
gen4asm.h is assembler specific while we want the library files to be
somewhat of a proper library.
This means that we have to redefine the GL* typedefs for brw_structs.h,
not using any of thet GL typedef will be for a future commit.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This allow us to factor out the test that checks if, when using both
predicates and conditional modifiers, we are using the same flag
register.
Also get rid of of a FIXME that we are now dealing with (the warning
mentioned above).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Like with the predicate fields before, there's no need to use the full
instruction to collect the list of options. This allows us to decouple
the list of options from a specific instruction encoding.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Right now we have duplicated code for when the option is the last in the
list or not. Put that code in a common function.
Interestingly it appears that both sides haven't been kept in sync and
that EOT and ACCWRCTRL had limitations on where they had to be in the
option list. It's fixed now!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Rather than user a full instruction for that. Also use
set_instruction_predicate() for a case that coud not be done like that
before the refactoring (because everyone now uses the same instruction
structure).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Now that all instructions (relocatable or not) are struct
brw_program_instructions, this means we can move the relocation specific
information out the "relocatable instruction" structure. This will allow
us to share the relocation information between different types of
instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This will be less typing for the refactoring to come (which is use
struct brw_program_instruction in gram.y for the type of all the
instructions).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Everything is now aligned to be able to use brw_set_src1() in the
opcode generation, so use it.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This way we ensure to have a single place where these are handled. The
immediate benefit is that now line numbers are always printed out, which
is quite handy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Unfortunately, it's all a walk in the park. Both, internal code in the
assembler and external shaders (libva) generate registers that trigger
assertions in brw_eu_emit.c's brw_validate().
To fix all that I took the option to be able to emit warning with the -W
flag but still make the assembler generate the same opcodes.
We can fix all this, but it requires validation, something that I cannot
do right now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Xiang, Haihao