In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
there're three Ports B/C/D used for selection by each transcoder A/B/C.
Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With the option '-r', the testdisplay could paint a 2-D bar code(QR
bar code) on the screen. The word "pass" is hiden in the bar code
image. Further more, with this option, testdisplay will wait until a
system signal 'SIGUSR1' coming after each mode setting. This function
is for another program to control testdisplay.
danvet: Fix up the missing static.
Signed-off-by: Yi Sun <yi.sun@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
When running autoreconf, it's possible to give flags to the underlying
aclocal by declaring a ACLOCAL_AMFLAGS variable in the top level
Makefile.am.
Putting ${ACLOCAL_FLAGS} there allows the user to set an environment
variable up before running autogen.sh and pull in the right directories
to look for m4 macros, say an up-to-date version of the xorg-util macros.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This will need to get modified when the ioctl expands, and so is only
here for reference/to make Daniel happy.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
By adding another testcase that follows up with a gpu read. This
checks whether the kernel properly tracks the pending write and
doesn't lose it (or sync up to the wrong seqno).
For some odd reason only the cpu mmap variant blows up, the gtt one
works here. I need to look into that some more.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This wraps libdrm functionality to exec with contexts. This patch
shouldn't be applied until libdrm for contexts is updated.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Due to the way we calculate the workload by doubling it each time we
might end up with almost twice as much as we want. Hence increase our
fudge by 1.5 to account for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50666
We need to hold forcewake lock in order to be able to read GT registers.
Otherwise, when the GPU is in RC6 mode, we'll read all zeros.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
When looking at the pwrite/pread/wc performance, it is useful to judge
that against the performance of an ordinary CPU mmap.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
