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https://github.com/tiagovignatti/intel-gpu-tools.git
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intel_audio_dump: add Haswell audio dump support
Add Haswell audio registers definition and dump support. Signed-off-by: Wang Xingchao <xingchao.wang@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Wang Xingchao
Daniel Vetter
parent
f9a2481e71
commit
c407722048
@ -94,6 +94,11 @@ static const char *dip_port[] = {
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[3] = "Digital Port D",
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};
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static const char *dip_type[] = {
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[0] = "Audio DIP Disabled",
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[1] = "Audio DIP Enabled",
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};
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static const char *dip_index[] = {
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[0] = "Audio DIP",
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[1] = "ACP DIP",
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@ -134,6 +139,17 @@ static const char *trans_to_port_sel[] = {
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[7] = "reserved",
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};
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static const char *ddi_mode[] = {
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[0] = "HDMI mode",
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[1] = "DVI mode",
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[2] = "DP SST mode",
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[3] = "DP MST mode",
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[4] = "DP FDI mode",
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[5] = "reserved",
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[6] = "reserved",
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[7] = "reserved",
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};
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static const char *transcoder_select[] = {
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[0] = "Transcoder A",
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[1] = "Transcoder B",
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@ -1354,6 +1370,569 @@ static void dump_cpt(void)
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}
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#undef AUD_CONFIG_A
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#undef AUD_MISC_CTRL_A
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#undef AUD_VID_DID
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#undef AUD_RID
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#undef AUD_CTS_ENABLE_A
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#undef AUD_PWRST
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#undef AUD_HDMIW_HDMIEDID_A
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#undef AUD_HDMIW_INFOFR_A
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#undef AUD_PORT_EN_HD_CFG
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#undef AUD_OUT_DIG_CNVT_A
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#undef AUD_OUT_STR_DESC_A
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#undef AUD_OUT_CH_STR
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#undef AUD_PINW_CONNLNG_LIST
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#undef AUD_CNTL_ST_A
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#undef AUD_HDMIW_STATUS
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#undef AUD_CONFIG_B
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#undef AUD_MISC_CTRL_B
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#undef AUD_CTS_ENABLE_B
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#undef AUD_HDMIW_HDMIEDID_B
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#undef AUD_HDMIW_INFOFR_B
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#undef AUD_OUT_DIG_CNVT_B
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#undef AUD_OUT_STR_DESC_B
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#undef AUD_CNTL_ST_B
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#undef AUD_CONFIG_C
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#undef AUD_MISC_CTRL_C
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#undef AUD_CTS_ENABLE_C
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#undef AUD_HDMIW_HDMIEDID_C
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#undef AUD_HDMIW_INFOFR_C
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#undef AUD_OUT_DIG_CNVT_C
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#undef AUD_OUT_STR_DESC_C
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#undef VIDEO_DIP_CTL_A
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#undef VIDEO_DIP_CTL_B
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#undef VIDEO_DIP_CTL_C
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#undef VIDEO_DIP_CTL_D
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#undef VIDEO_DIP_DATA
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/*
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* Haswell registers
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*/
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/* DisplayPort Transport Control */
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#define DP_TP_CTL_A 0x64040
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#define DP_TP_CTL_B 0x64140
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#define DP_TP_CTL_C 0x64240
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#define DP_TP_CTL_D 0x64340
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#define DP_TP_CTL_E 0x64440
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/* DisplayPort Transport Status */
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#define DP_TP_ST_A 0x64044
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#define DP_TP_ST_B 0x64144
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#define DP_TP_ST_C 0x64244
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#define DP_TP_ST_D 0x64344
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#define DP_TP_ST_E 0x64444
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/* Transcoder configuration */
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#define TRANS_CONF_A 0xF0008
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#define TRANS_CONF_B 0xF1008
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#define TRANS_CONF_C 0xF2008
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/* DDI Buffer Control */
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#define DDI_BUF_CTL_A 0x64000
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#define DDI_BUF_CTL_B 0x64100
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#define DDI_BUF_CTL_C 0x64200
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#define DDI_BUF_CTL_D 0x64300
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#define DDI_BUF_CTL_E 0x64400
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/* DDI Buffer Translation */
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#define DDI_BUF_TRANS_A 0x64e00
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#define DDI_BUF_TRANS_B 0x64e60
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#define DDI_BUF_TRANS_C 0x64ec0
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#define DDI_BUF_TRANS_D 0x64f20
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#define DDI_BUF_TRANS_E 0x64f80
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/* DDI Aux Channel */
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#define DDI_AUX_CHANNEL_CTRL 0x64010
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#define DDI_AUX_DATA 0x64014
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#define DDI_AUX_TST 0x64028
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/* DDI CRC Control */
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#define DDI_CRC_CTL_A 0x64050
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#define DDI_CRC_CTL_B 0x64150
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#define DDI_CRC_CTL_C 0x64250
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#define DDI_CRC_CTL_D 0x64350
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#define DDI_CRC_CTL_E 0x64450
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/* Pipe DDI Function Control */
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#define PIPE_DDI_FUNC_CTL_A 0x60400
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#define PIPE_DDI_FUNC_CTL_B 0x61400
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#define PIPE_DDI_FUNC_CTL_C 0x62400
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#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
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/* Pipe Configuration */
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#define PIPE_CONF_A 0x70008
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#define PIPE_CONF_B 0x71008
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#define PIPE_CONF_C 0x72008
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#define PIPE_CONF_EDP 0x7F008
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/* Audio registers */
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#define AUD_CONFIG_A 0x65000
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#define AUD_MISC_CTRL_A 0x65010
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#define AUD_VID_DID 0x65020
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#define AUD_RID 0x65024
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#define AUD_CTS_ENABLE_A 0x65028
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#define AUD_PWRST 0x6504C
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#define AUD_HDMIW_HDMIEDID_A 0x65050
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#define AUD_HDMIW_INFOFR_A 0x65054
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#define AUD_PORT_EN_HD_CFG 0x6507C
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#define AUD_OUT_DIG_CNVT_A 0x65080
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#define AUD_OUT_STR_DESC_A 0x65084
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#define AUD_OUT_CHAN_MAP 0x65088
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#define AUD_PINW_CONNLNG_LIST_A 0x650A8
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#define AUD_PINW_CONNLNG_LIST_B 0x651A8
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#define AUD_PINW_CONNLNG_LIST_C 0x652A8
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#define AUD_PIPE_CONN_SEL_CTRL 0x650AC
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#define AUD_PIN_ELD_CP_VLD 0x650C0
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#define AUD_HDMIW_STATUS 0x650D4
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#define AUD_CONFIG_B 0x65100
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#define AUD_MISC_CTRL_B 0x65110
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#define AUD_CTS_ENABLE_B 0x65128
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#define AUD_HDMIW_HDMIEDID_B 0x65150
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#define AUD_HDMIW_INFOFR_B 0x65154
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#define AUD_OUT_DIG_CNVT_B 0x65180
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#define AUD_OUT_STR_DESC_B 0x65184
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#define AUD_CONFIG_C 0x65200
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#define AUD_MISC_CTRL_C 0x65210
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#define AUD_CTS_ENABLE_C 0x65228
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#define AUD_HDMIW_HDMIEDID_C 0x65250
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#define AUD_HDMIW_INFOFR_C 0x65254
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#define AUD_OUT_DIG_CNVT_C 0x65280
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#define AUD_OUT_STR_DESC_C 0x65284
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#define AUD_DIP_ELD_CTRL_ST_A 0x650b4
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#define AUD_DIP_ELD_CTRL_ST_B 0x651b4
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#define AUD_DIP_ELD_CTRL_ST_C 0x652b4
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/* Video DIP Control */
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#define VIDEO_DIP_CTL_A 0x60200
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#define VIDEO_DIP_CTL_B 0x61200
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#define VIDEO_DIP_CTL_C 0x62200
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#define VIDEO_DIP_CTL_D 0x63200
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#define VIDEO_DIP_DATA 0x60220
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#define VIDEO_DIP_ECC 0x60240
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#define AUD_DP_DIP_STATUS 0x65f20
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static void dump_hsw(void)
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{
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uint32_t dword;
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int i;
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/* HSW DDI Buffer */
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dump_reg(DDI_BUF_CTL_A, "DDI Buffer Controler A");
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dump_reg(DDI_BUF_CTL_B, "DDI Buffer Controler B");
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dump_reg(DDI_BUF_CTL_C, "DDI Buffer Controler C");
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dump_reg(DDI_BUF_CTL_D, "DDI Buffer Controler D");
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dump_reg(DDI_BUF_CTL_E, "DDI Buffer Controler E");
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/* HSW Pipe Function */
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dump_reg(PIPE_CONF_A, "PIPE Configuration A");
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dump_reg(PIPE_CONF_B, "PIPE Configuration B");
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dump_reg(PIPE_CONF_C, "PIPE Configuration C");
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dump_reg(PIPE_CONF_EDP, "PIPE Configuration EDP");
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dump_reg(PIPE_DDI_FUNC_CTL_A, "PIPE DDI Function Control A");
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dump_reg(PIPE_DDI_FUNC_CTL_B, "PIPE DDI Function Control B");
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dump_reg(PIPE_DDI_FUNC_CTL_C, "PIPE DDI Function Control C");
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dump_reg(PIPE_DDI_FUNC_CTL_EDP, "PIPE DDI Function Control EDP");
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/* HSW Display port */
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dump_reg(DP_TP_CTL_A, "DisplayPort Transport A Control");
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dump_reg(DP_TP_CTL_B, "DisplayPort Transport B Control");
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dump_reg(DP_TP_CTL_C, "DisplayPort Transport C Control");
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dump_reg(DP_TP_CTL_D, "DisplayPort Transport D Control");
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dump_reg(DP_TP_CTL_E, "DisplayPort Transport E Control");
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dump_reg(DP_TP_ST_A, "DisplayPort Transport A Status");
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dump_reg(DP_TP_ST_B, "DisplayPort Transport B Status");
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dump_reg(DP_TP_ST_C, "DisplayPort Transport C Status");
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dump_reg(DP_TP_ST_D, "DisplayPort Transport D Status");
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dump_reg(DP_TP_ST_E, "DisplayPort Transport E Status");
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/* HSW Transcoder A configuration */
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dump_reg(TRANS_CONF_A, "Transcoder A Configuration");
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dump_reg(TRANS_CONF_B, "Transcoder B Configuration");
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dump_reg(TRANS_CONF_C, "Transcoder C Configuration");
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/* HSW North Display Audio */
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dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
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dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
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dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
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dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
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dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
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dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
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dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
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dump_reg(AUD_RID, "Audio Revision ID");
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dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
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dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
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dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
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dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
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dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
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dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
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dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
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dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
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dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
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dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
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dump_reg(AUD_PORT_EN_HD_CFG, "Audio Pipe and Convert Configs");
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dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
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dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
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dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
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dump_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping");
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dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
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dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
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dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
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dump_reg(AUD_PINW_CONNLNG_LIST_A, "Audio Connection List entry and Length - Transcoder A");
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dump_reg(AUD_PINW_CONNLNG_LIST_B, "Audio Connection List entry and Length - Transcoder B");
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dump_reg(AUD_PINW_CONNLNG_LIST_C, "Audio Connection List entry and Length - Transcoder C");
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dump_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control");
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dump_reg(AUD_DIP_ELD_CTRL_ST_A, "Audio DIP and ELD control state - Transcoder A");
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dump_reg(AUD_DIP_ELD_CTRL_ST_B, "Audio DIP and ELD control state - Transcoder B");
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dump_reg(AUD_DIP_ELD_CTRL_ST_C, "Audio DIP and ELD control state - Transcoder C");
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dump_reg(AUD_PIN_ELD_CP_VLD, "audio pin eld valid status");
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dump_reg(AUD_HDMIW_STATUS, "Audio HDMI FIFO Status");
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printf("\nDetails:\n\n");
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dword = INREG(AUD_VID_DID);
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printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
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printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
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dword = INREG(AUD_RID);
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printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
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printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
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printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
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printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
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dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
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printf("Audio DIP and ELD control state for TranscoderA\n");
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printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
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printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
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printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
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printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
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printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
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printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
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dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
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printf("Audio DIP and ELD control state for TranscoderB\n");
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printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
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printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
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printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
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printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
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printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
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printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
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dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
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printf("Audio DIP and ELD control state for TranscoderC\n");
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printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
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printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
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printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
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printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
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printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
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printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
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dword = INREG(DDI_BUF_CTL_A);
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printf("DDI A Buffer control\n");
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printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
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printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
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dword = INREG(DDI_BUF_CTL_B);
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printf("DDI B Buffer control\n");
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printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
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printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
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dword = INREG(DDI_BUF_CTL_C);
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printf("DDI C Buffer control\n");
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printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
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printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
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dword = INREG(DDI_BUF_CTL_D);
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printf("DDI D Buffer control\n");
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printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
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printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
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BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
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dword = INREG(DDI_BUF_CTL_E);
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printf("DDI E Buffer control\n");
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printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
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printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
|
||||
BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
|
||||
|
||||
dword = INREG(PIPE_DDI_FUNC_CTL_A);
|
||||
printf("Pipe A DDI Function Control\n");
|
||||
printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
|
||||
printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
|
||||
trans_to_port_sel[BITS(dword, 30, 28)]);
|
||||
printf("PIPE DDI Mode\t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
|
||||
printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
|
||||
|
||||
dword = INREG(PIPE_DDI_FUNC_CTL_B);
|
||||
printf("Pipe B DDI Function Control\n");
|
||||
printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
|
||||
printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
|
||||
trans_to_port_sel[BITS(dword, 30, 28)]);
|
||||
printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
|
||||
printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
|
||||
|
||||
dword = INREG(PIPE_DDI_FUNC_CTL_C);
|
||||
printf("Pipe C DDI Function Control\n");
|
||||
printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
|
||||
printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
|
||||
trans_to_port_sel[BITS(dword, 30, 28)]);
|
||||
printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
|
||||
printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
|
||||
|
||||
dword = INREG(AUD_CONFIG_A);
|
||||
printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
|
||||
n_index_value[BIT(dword, 29)]);
|
||||
printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
|
||||
printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
|
||||
printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
|
||||
printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
|
||||
OPNAME(pixel_clock, BITS(dword, 19, 16)));
|
||||
printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
dword = INREG(AUD_CONFIG_B);
|
||||
printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
|
||||
n_index_value[BIT(dword, 29)]);
|
||||
printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
|
||||
printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
|
||||
printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
|
||||
printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
|
||||
OPNAME(pixel_clock, BITS(dword, 19, 16)));
|
||||
printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
dword = INREG(AUD_CONFIG_C);
|
||||
printf("AUD_CONFIG_C N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
|
||||
n_index_value[BIT(dword, 29)]);
|
||||
printf("AUD_CONFIG_C N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
|
||||
printf("AUD_CONFIG_C Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
|
||||
printf("AUD_CONFIG_C Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
|
||||
printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
|
||||
OPNAME(pixel_clock, BITS(dword, 19, 16)));
|
||||
printf("AUD_CONFIG_C Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
|
||||
dword = INREG(AUD_CTS_ENABLE_A);
|
||||
printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
|
||||
printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
|
||||
printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
|
||||
dword = INREG(AUD_CTS_ENABLE_B);
|
||||
printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
|
||||
printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
|
||||
printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
|
||||
dword = INREG(AUD_CTS_ENABLE_C);
|
||||
printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
|
||||
printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
|
||||
printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
|
||||
|
||||
dword = INREG(AUD_MISC_CTRL_A);
|
||||
printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
|
||||
printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
|
||||
printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
dword = INREG(AUD_MISC_CTRL_B);
|
||||
printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
|
||||
printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
|
||||
printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
dword = INREG(AUD_MISC_CTRL_C);
|
||||
printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
|
||||
printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
|
||||
printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
|
||||
dword = INREG(AUD_PWRST);
|
||||
printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
|
||||
printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
|
||||
printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
|
||||
printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
|
||||
printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
|
||||
printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
|
||||
printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
|
||||
printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
|
||||
printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
|
||||
printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
|
||||
printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
|
||||
printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
|
||||
printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
|
||||
printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
|
||||
|
||||
dword = INREG(AUD_PORT_EN_HD_CFG);
|
||||
printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
|
||||
printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
|
||||
printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
|
||||
printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
|
||||
printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
|
||||
printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
|
||||
|
||||
dword = INREG(AUD_OUT_DIG_CNVT_A);
|
||||
printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
|
||||
printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
|
||||
printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
|
||||
printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
|
||||
printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
|
||||
printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
|
||||
printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
|
||||
|
||||
dword = INREG(AUD_OUT_DIG_CNVT_B);
|
||||
printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
|
||||
printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
|
||||
printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
|
||||
printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
|
||||
printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
|
||||
printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
|
||||
printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
|
||||
|
||||
dword = INREG(AUD_OUT_DIG_CNVT_C);
|
||||
printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
|
||||
printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
|
||||
printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
|
||||
printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
|
||||
printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
|
||||
printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
|
||||
printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n",BITS(dword, 19, 16));
|
||||
printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
|
||||
|
||||
printf("AUD_OUT_CHAN_MAP Converter_Channel_MAP PORTB PORTC PORTD\n");
|
||||
for (i = 0; i < 8; i++) {
|
||||
OUTREG(AUD_OUT_CHAN_MAP, i | (i << 8) | (i << 16));
|
||||
dword = INREG(AUD_OUT_CHAN_MAP);
|
||||
printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
|
||||
1 + BITS(dword, 3, 0),
|
||||
1 + BITS(dword, 7, 4),
|
||||
1 + BITS(dword, 15, 12),
|
||||
1 + BITS(dword, 23, 20));
|
||||
}
|
||||
|
||||
dword = INREG(AUD_OUT_STR_DESC_A);
|
||||
printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
|
||||
printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
|
||||
BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
|
||||
printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
|
||||
|
||||
dword = INREG(AUD_OUT_STR_DESC_B);
|
||||
printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
|
||||
printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
|
||||
BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
|
||||
printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
|
||||
|
||||
dword = INREG(AUD_OUT_STR_DESC_C);
|
||||
printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
|
||||
printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
|
||||
BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
|
||||
printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
|
||||
|
||||
dword = INREG(AUD_PINW_CONNLNG_SEL);
|
||||
printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
|
||||
printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
|
||||
printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
|
||||
|
||||
dword = INREG(AUD_PIN_ELD_CP_VLD);
|
||||
printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
|
||||
printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
|
||||
printf("AUD_CNTRL_ST2 OUT_enableB\t\t\t\t%lu\n", BIT(dword, 2));
|
||||
printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
|
||||
printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
|
||||
printf("AUD_CNTRL_ST2 OUT_enableC\t\t\t\t%lu\n", BIT(dword, 6));
|
||||
printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
|
||||
printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
|
||||
printf("AUD_CNTRL_ST2 OUT_enableD\t\t\t\t%lu\n", BIT(dword, 10));
|
||||
|
||||
dword = INREG(AUD_HDMIW_STATUS);
|
||||
printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
|
||||
printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
|
||||
printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
|
||||
printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
|
||||
printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
|
||||
printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
|
||||
printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
|
||||
printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
|
||||
|
||||
printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
|
||||
dword &= ~BITMASK(9, 5);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
|
||||
for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
|
||||
printf("\n");
|
||||
|
||||
printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
|
||||
dword &= ~BITMASK(9, 5);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
|
||||
for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
|
||||
printf("\n");
|
||||
|
||||
printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
|
||||
dword &= ~BITMASK(9, 5);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
|
||||
for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
|
||||
printf("\n");
|
||||
|
||||
printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
|
||||
dword &= ~BITMASK(20, 18);
|
||||
dword &= ~BITMASK(3, 0);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
|
||||
for (i = 0; i < 8; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
|
||||
printf("\n");
|
||||
|
||||
printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
|
||||
dword &= ~BITMASK(20, 18);
|
||||
dword &= ~BITMASK(3, 0);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
|
||||
for (i = 0; i < 8; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
|
||||
printf("\n");
|
||||
|
||||
printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
|
||||
dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
|
||||
dword &= ~BITMASK(20, 18);
|
||||
dword &= ~BITMASK(3, 0);
|
||||
OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
|
||||
for (i = 0; i < 8; i++)
|
||||
printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
struct pci_device *pci_dev;
|
||||
@ -1369,6 +1948,11 @@ int main(int argc, char **argv)
|
||||
intel_get_mmio(pci_dev);
|
||||
|
||||
if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
|
||||
if (IS_HASWELL(devid)) {
|
||||
printf("Haswell audio registers:\n\n");
|
||||
dump_hsw();
|
||||
return 0;
|
||||
}
|
||||
printf("%s audio registers:\n\n",
|
||||
IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
|
||||
intel_check_pch();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user