In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
We should get more kms tests soon, and not needing to copy-paste a
nice test pattern should be useful.
That establishes a firm depency of i-g-t on cairo over everything, but
I don't care so much about that.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Headers are found under top_srcdir/...
Headers are CPP flags, not C Flags
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Gaetan Nadon <memsize@videotron.ca>
Use CWARNFLAGS as in all of xorg. There seems to be no reason why this
module should be different. The warnings were updated recently
for those who install the latest util-macros.
Signed-off-by: Gaetan Nadon <memsize@videotron.ca>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
A few of the tools can be performed post-mortem from a different system,
so it is useful to be able to compile those tools on those foreign
systems. Obviously, any program to interact with the PCI device or talk
to GEM will fail on a non-Intel system.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
