Until now, the assembler had relocation-related fields added to struct
brw_instruction. This changes the size of the structure and break code
assuming the opcode structure is really 16 bytes, for instance the
emission code in brw_eu_emit.c.
With this commit, we build on the infrastructure that slowly emerged in
the few previous commits to add a relocatable instruction with the
needed fields.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The output of the parsing is a list of struct brw_program_instruction.
These instructions can be either GEN instructions aka struct
brw_instruction or labels. To make this more explicit we now have a type
to test to determine which instruction we are dealing with.
This will also allow to to pull the relocation bits into struct
brw_program_instruction instead of having them in the structure
representing the opcodes.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Factoring out the code from the grammar will allow us to switch to
using brw_compile in a cleaner way.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
No need to use a brw_program_instruction there as a brw_instruction is
what you really dump anyway, espcially when the plan is to use
brw_compile from Mesa sooner rather than later.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This function can only be called to resolve subreg_nr in direct mode
(there is an other function for the indirect case) and it makes no sense
to call it with an immediate operand.
Express those facts with asserts and simplify the logic.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Another step towards using struct brw_reg for source and destination
operands.
Instead of having a separate field to store the sub register number of
the address register in indirect access mode, we can reuse the subreg_nr
field that was only used for direct access so far.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
writemask_set gets in the way of switching to using struct brw_reg and
it's possible to derive it from the writemask value.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
To be able to import brw_eu.c and brw_eu_emit.c later on. This could be
used to get the assembler generate compact instructions at some point.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
With the brw_* files imported from mesa.
There are still a few things in that library that needs gen4asm.h, for
instance the GLuint and GLint types. The hope is that eventually libbrw
can be split out in its own directory and shared.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
A lot of the mesa code use struct brw_context to get the GPU generation
and various information. Let's stub this structure and initialize it
ourselves to be able to resuse mesa's code untouched.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
This also add a new brw_compat.h that should help maintaining the
diff between mesa's version and our as small as possible.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
From Mesa. This imports a bit more the of brw_eu* infrastructure (which
is going towards the right direction!) from mesa and the update is quite
a significant improvement over what we had.
I also verified that the changes that were done on the assembler old
version of brw_disasm.c were already supported by the Mesa version, and
indeed they were.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Finally merge both brw_structs.h from mesa. One detail has risen in that
last commit, the msg_control field of data port message descriptors.
Mesa's msg_control field is sometimes split with messages-specific
fields where the assembler (at least for recent generations) exposes the
full msg_control value in the send instruction.
As libva's shaders encodes the full msg_control value in its send
instructions, I've chosen to not take the split msg_control from mesa.
It's absolutely possible to have a patch fixing that divergence at some
later point.
I've also kept a hack introduced with ironlake to not have to rewrite
shaders (that encode msg_control in the text, remember), and thus
creates a another difference with Mesa.
- GLuint msg_control:3;
- GLuint msg_type:3;
+ GLuint msg_control:4;
+ GLuint msg_type:2;
Once again, I've made sure that re-generating libva's shaders don't show
any difference.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
We ended up with 2 structures that where exactly the same, so just use
one, which happens to be the one Mesa has.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
I had to drop how mesa splits msg_control as the current assembly
language gives access the the whole msg_control field.
Recompiling the xorg and the intel driver of libva shaders doesn't show
any difference in the assembly created.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
I had to drop how mesa splits msg_control as the current assembly
language gives access the the whole msg_control field.
Recompiling the xorg and the intel driver of libva shaders doesn't show
any difference in the assembly created.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Two changes there, a field has been renamed and one bit of padding is
now used for compressed instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Add new helper macros to check versions:
- IS_GENp() meant to match Gen X and above
- IS_GENx() meant to match Gen X exactly.
Patch mechanically generated. No stale "gen_level" usage.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
