8 Commits

Author	SHA1	Message	Date
Damien Lespiau	4ca1a04b85	assembler: Update the disassembler code ... From Mesa. This imports a bit more the of brw_eu* infrastructure (which is going towards the right direction!) from mesa and the update is quite a significant improvement over what we had. I also verified that the changes that were done on the assembler old version of brw_disasm.c were already supported by the Mesa version, and indeed they were. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>	2013-03-04 15:54:37 +00:00
Damien Lespiau	191c85976d	build: Integrate the merged gen assembler in the build system ... Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>	2013-03-04 15:54:35 +00:00
Eric Anholt	9b40c3724a	Add autotools build system, and rearrange directory layout.	2013-03-04 15:54:23 +00:00
Eric Anholt	3bcf6b29cd	Add support for register-indirect access in destination registers. ... This is untested. Also, a few bits for source operand register-indirect access sneak in with this commit.	2013-03-04 15:54:23 +00:00
Eric Anholt	2dac0a19a4	Add support for destination writemasks. ... This involved changing dest operands to have their own structure like src operands, as the destination writemask (which is align16-only) shares space with register numbers in align1 mode.	2013-03-04 15:54:23 +00:00
Eric Anholt	6a88ada7e8	Add support for swizzle control on source operands. ... This required restructuring to store source operands in a new structure rather than being stored in instructions, as swizzle is align16-only and shares storage with other fields for align1 mode. These changes were not tested on real programs using swizzle.	2013-03-04 15:54:22 +00:00
Eric Anholt	f2f18561e5	C warnings cleanup.	2013-03-04 15:54:20 +00:00
Eric Anholt	22a1063cc0	Initial gen4asm code.	2013-03-04 15:54:20 +00:00