flywithu/ntel-gpu-tools
1
0
Fork 0
mirror of https://github.com/tiagovignatti/intel-gpu-tools.git synced 2025-06-08 08:26:10 +00:00
Code Issues Releases Wiki Activity
1,165 Commits 13 Branches 0 Tags
Commit Graph

224 Commits

Author SHA1 Message Date
Damien Lespiau
1f1ad59746 assembler: Rename dp_gen6 to gen6_dp and sync with Mesa's 
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.

I had to drop how mesa splits msg_control as the current assembly
language gives access the the whole msg_control field.

Recompiling the xorg and the intel driver of libva shaders doesn't show
any difference in the assembly created.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:36 +00:00
Damien Lespiau
668e0dff7d assembler: Rename dp_read_gen6 to gen6_dp_sampler_const_cache 
The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:36 +00:00
Damien Lespiau
31259c5edc assembler: Rename three_src_gen6 to da3src 
Mesa's brw_structs.h has named/renamed this field to da3src. Sync with
them.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:36 +00:00
Damien Lespiau
e71f1d2ad4 assembler: Sync brw_instruction's header with mesa's 
Two changes there, a field has been renamed and one bit of padding is
now used for compressed instructions.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:35 +00:00
Damien Lespiau
191c85976d build: Integrate the merged gen assembler in the build system 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2013-03-04 15:54:35 +00:00
Xiang, Haihao
e466360df9 bump version to 1.3 
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 2013-03-04 15:54:35 +00:00
Homer Hsing
5d72789848 Fix typo. "donesn't" -> "doesn't" 2013-03-04 15:54:35 +00:00
Zhao Yakui
93f2a4fc93 Add the CRE enginee for HSW+ 
This is also for media encoding like VME, which can do
the operation of check & refinement.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 2013-03-04 15:54:35 +00:00
Gwenole Beauchesne
495c4e14e7 Fix JMPI encoding for Haswell. 
It uses the byte-aligned jump instead of 64-bit units.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 2013-03-04 15:54:35 +00:00
Gwenole Beauchesne
8aa952873c Add initial support for Haswell. 
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 2013-03-04 15:54:35 +00:00
Gwenole Beauchesne
0c32e25c96 Allow Gen version decimals. 
This is preparatory work for Haswell (Gen 7.5).

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
 2013-03-04 15:54:35 +00:00
Gwenole Beauchesne
a5e5d94ce3 Bump gen_level to multiple of tens. 
Add new helper macros to check versions:
- IS_GENp() meant to match Gen X and above
- IS_GENx() meant to match Gen X exactly.

Patch mechanically generated. No stale "gen_level" usage.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 2013-03-04 15:54:35 +00:00
Homer Hsing
ee32188422 Fix Gen7 JMPI compilation 
Gen7 JMPI Restrictions in bspec:
The JIP data type must be Signed DWord
 2013-03-04 15:54:34 +00:00
Homer Hsing
e221b0aa78 Fix sub-register number of an address register encoding 
The AddrSubRegNum field in the instruction binary code should be:
  code    value(advanced_flag==0)   value(advanced_flag==1)
  a0.0             0                         0
  a0.1        invalid input                  1
  a0.2             1                         2
  a0.3        invalid input                  3
  a0.4             2                         4
  a0.5        invalid input                  5
  a0.6             3                         6
  a0.7        invalid input                  7
  a0.8             4                  invalid input
  a0.10            5                  invalid input
  a0.12            6                  invalid input
  a0.14            7                  invalid input
 2013-03-04 15:54:34 +00:00
Homer Hsing
599d7d244a Fix symbol register subreg number calculation rule symbol_reg_p 
When in normal mode, subreg_nr should not be divided by type_size.
This patch fixes such bug.
 2013-03-04 15:54:34 +00:00
Homer Hsing
460fdc041b Show warning when compiling the grammar parser 2013-03-04 15:54:34 +00:00
Homer Hsing
e8cb195c6d Support Gen6 WHILE instruction 2013-03-04 15:54:34 +00:00
Homer Hsing
2ad18c1c97 Make sure Gen6 IF works 2013-03-04 15:54:34 +00:00
Homer Hsing
c56d786116 Make sure Gen6 ENDIF work 2013-03-04 15:54:34 +00:00
Homer Hsing
397e1ccccb Fix JIP position for Gen6 JMPI 2013-03-04 15:54:34 +00:00
Homer Hsing
c91bd8c76f Fix Gen6 ELSE instructions code logic according to bspec. 2013-03-04 15:54:34 +00:00
Homer Hsing
ce55552470 Make sure BREAK/CONT/HALT work on Gen6. 2013-03-04 15:54:34 +00:00
Homer Hsing
3de439e2f5 Support Gen6 RET instruction. 2013-03-04 15:54:34 +00:00
Homer Hsing
7529682d0a Support Gen6 CALL instruction. 2013-03-04 15:54:34 +00:00
Homer Hsing
b899aba57f Replace variable init code in WAIT by src_null_reg 2013-03-04 15:54:34 +00:00
Homer Hsing
7e2461b6fc Let ip_dst and ip_src become local const variable, so as to reduce replicated code. 2013-03-04 15:54:34 +00:00
Homer Hsing
45ab3cf5a1 Support Gen6 three-source-operand instructions. 
Add bits1.three_src.gen6.dest_reg_file according to Gen6 spec
 2013-03-04 15:54:33 +00:00
Homer Hsing
72a3c194db Compile ELSE and WHILE in Gen5 as same way as in Gen4 2013-03-04 15:54:33 +00:00
Homer Hsing
f55ed65bb2 Fix reloc_target_offset computing logic 2013-03-04 15:54:33 +00:00
Homer Hsing
4bf84ec146 Fully support Gen7 branching instructions 
Also fix integer argument parsing rule for JMPI, IF and WHILE
Fix shift/reduce conflicts in relativelocation
 2013-03-04 15:54:33 +00:00
Homer Hsing
88dfdf34df Supporting multi-branch instructios BRD & BRC 
brd: redirect channels to branches
brc: let channels converging together

also rewrite code converting label to offset
 2013-03-04 15:54:33 +00:00
Homer Hsing
5d589dbe13 Use right-recursing in parser rule inst_option_list 
This recursing cost less memory. It is recommended by Bison.
 2013-03-04 15:54:33 +00:00
Homer Hsing
a7b1c09d18 Support subroutine instructions, CALL & RET 2013-03-04 15:54:33 +00:00
Homer Hsing
c0ebde2786 Merge replicative code in gram.y 2013-03-04 15:54:33 +00:00
Homer Hsing
b0b540f02a Reduce replicative code in gram.y by reloc_target field in src_operand 
Bspec says JIP and UIP should be the source operands. It is better if
src_operand has a field "reloc_target" according to bspec.
The replicative code in JMPI and branchloop rules can be merged into one.
 2013-03-04 15:54:33 +00:00
Homer Hsing
1f9a4d71e8 Restrict type of relativelocation2 to int 
Original rule set it to EXP | NUMBER, then YYERROR if it is NUMBER.
This patch set it directly to EXP, restricting its type to int.
 2013-03-04 15:54:33 +00:00
Homer Hsing
ccd1721190 Rewrite label matching code. Collect labels in a linked list. 
Label matching is faster because of searching only in a small list,
rather than searching a label in all instructions.
 2013-03-04 15:54:33 +00:00
Homer Hsing
751838e809 Add second_reloc_target in the data structure. 
Since Gen6+, some branching instructions have two relocation targets.
 2013-03-04 15:54:33 +00:00
Homer Hsing
d6f02c181f Add test case for ".declare" overriding feature. 
Later same name .declare pragma will override previously defined
one. This patch add a test case for that feature.
 2013-03-04 15:54:33 +00:00
Homer Hsing
2ab4c0d9b8 Fix memory leaking in the parser 
STRING has been malloc'ed by strdup in src/lex.l but forgotten to
be freed in src/gram.y.
 2013-03-04 15:54:33 +00:00
Homer Hsing
741008e050 Fix field length of JIP for one-offset-branch in Gen6 
Such JIP has 25 bits length in Gen6.
 2013-03-04 15:54:33 +00:00
Homer Hsing
6983eebf47 Automatically run all test cases. 
In the past test/run-test.sh run only one test case per call.
This patch let it automatically run all test cases.
 2013-03-04 15:54:32 +00:00
Homer Hsing
1c009349bc Fix missing environment variables problem in test/run-test.sh 
Currently test/run-test.sh cannot get the value of ${srcdir} and
${top_builddir}. Thus we cannot run any test case. This patch uses
$0 to get the absolute path of run-test.sh. Now test cases work.
 2013-03-04 15:54:32 +00:00
Homer Hsing
868cbf7dc5 Add a generic hash table algorithm. Reuse for declared_reg_table and label_table in the future. 
Rewrite find_register() and insert_register(). The hash table code
has been extracted. We may use those code for label table in the future.
 2013-03-04 15:54:32 +00:00
Homer Hsing
131f61f2ef Add a test case for ".declare" pragma 2013-03-04 15:54:32 +00:00
Homer Hsing
c3bcc7dbeb Rename brw_instruction.bits3.if_else to branch 
Because that field will be used for all branch instructions
 2013-03-04 15:54:32 +00:00
Homer Hsing
bebe8179e1 According to BSPEC, put PLN & BFI1 to binaryop, put SUBB to binaryaccop 
bspec: BFI1 should not access accumulator. PLN should not use accumulator
as source.
future work in gram.y: show warning if acc is used as dest for
ADDC/SUBB/CMP/CMPN/SHL/BFI1.
 2013-03-04 15:54:32 +00:00
Homer Hsing
74383f4db4 Explain the difference between binaryinstruction and binaryaccinstruction 
Developers may add new instructions in wrong place in the future
if they don't know the difference between binaryinstruction and
binaryaccinstruction.
 2013-03-04 15:54:32 +00:00
Homer Hsing
375d1fd7b2 Renaming according to BSPEC: jump_count -> JIP; pop_count -> UIP. 
Since bspec SNB+, jump_count and pop_count is renamed to JIP and uIP.
 2013-03-04 15:54:32 +00:00
Homer Hsing
6171c61e0c Use bits3.if_else.jump_count instead of bits3.ud for readability 2013-03-04 15:54:32 +00:00