With the header cleanup we can now give this header a suitable name,
since it now really only contains register access and other I/O
functions and assorted definitions.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This provides a macro that allows us to update all the arbitrary blit
commands we have stuck throughout the code. It assumes we don't actually
use 64b relocs (which is currently true). This also allows us to easily find
all the areas we need to update later when we really use the upper dword.
This block was done mostly with a sed job, and represents the easier
in test blit implementations.
v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
A few of the tools can be performed post-mortem from a different system,
so it is useful to be able to compile those tools on those foreign
systems. Obviously, any program to interact with the PCI device or talk
to GEM will fail on a non-Intel system.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Add four new tests for error the error handling cases:
- gem_bad_address - store to a bad address, should generate a protection or
page table error
- gem_bad_batch - try to execute a bad batch, should generate a protection,
invalid instruction or page table error
- gem_bad_blit - blit to an invalid location, should generated a protection
or page table error
- gem_hang - hang the GPU on an event that will never happen, test hang
detection & recovery code
