This was originally part of:
commit 62298329350b965e4bbfc558e5a4b1b3646742ea
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Aug 14 14:21:16 2013 -0700
assembler: error for the wrong syntax of SEND instruction on GEN6+
I merged that patch separately, but this tiny hunk was leftover. In
order to not muck in changing too much history, I am leaving this as a
discrete patch, but with the changed commit message
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Still some work needed there, but enough for rendercopy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This allows to use the same functions to validate operands on gen8 for
now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
We should now support alu2 intructions with direct register addressing.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
The code is from the storedw_loop_render.
v2 (by Ben): Flush on the correct ring
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
The code is from the storedw_loop_render.
v2 (by Ben): Flush on the correct Ring
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This provides a macro that allows us to update all the arbitrary blit
commands we have stuck throughout the code. It assumes we don't actually
use 64b relocs (which is currently true). This also allows us to easily find
all the areas we need to update later when we really use the upper dword.
This block was done mostly with a sed job, and represents the easier
in test blit implementations.
v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Check on debugfs if PSR is supported by panel and matching all conditions in
hardware. In this case PSR must be enabled and performance counting increasing
v2: check if performance counter is really increasing.
v3: respect new naming convention
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
This helps make sure that the GPU is really quiescent by getting
rid of any residual stuff.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Same thing that was done for prime_self_import.
v2: Move igt_drop_caches_set() call inside get_object_count() to make
it clearer why we want this.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
We don't want a previously used object to be freed in the middle of a
before/after object counting operation (or we would get a "-1 objects
leaked" message). We have seen this happening, e.g., when a context
from a previous run dies, but its backing object is alive waiting for
a retire_work to kick in.
v2: Use igt_debugfs facilities for drop cache.
v3: Move igt_drop_caches_set() call inside get_object_count() to make
it clearer why we want this.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
I was a bit on the fence about the basic pipe CRC test since that
doesn't really test kms, but debug infrastructure in debugfs.
Otoh running this one for a full kms testrun is always good, to make
sure that all the other (real) CRC based tests work sanely.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imo power management, power consumption and performance are tightly
enough coupled that we can throw them all into one bin.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Just a start and we need more work here. Some follow-up patches will
clear up some of the historical confusion.
While at it rename the pc8 "basic" test to "rte".
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This is basically a "drop cache" interface to the igt_debugfs
facilities. Also, update existing users.
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
