2056 Commits

Author SHA1 Message Date
Daniel Vetter
4cf1d089eb tests/gem_reloc_overflow: Polish after Rafael's patch
- use void* for generic pointer.
- Fix const usage.
- Shut up gcc about uninitizialized var.
- Be paranoid about the moved tests and make double-sure that the
  batch would indeed work safe for the condition being tested.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 13:43:43 +01:00
Rafael Barbalho
c537c23efc tests/gem_reloc_overflow: Add gen8+ specifc tests
Broadwell introduces 64-bit relocation addresses which add extra
corner cases. The test was refactored slightly with some tests that
were in the source offset tests were moved to the more generic reloc
test area. The source offset tests are now gen aware and called twice to
test both cpu & gtt relocation paths. In addition 2 new gen8+ test
were added to the test:

* Relocation straddling page a page
* Insufficient space for a relocation at the end of the buffer.

Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>

Conflicts:
	tests/gem_reloc_overflow.c
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 13:41:38 +01:00
Daniel Vetter
5fab0b8aa7 NEWS: Remove spurious -
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06 18:55:20 +01:00
Ben Widawsky
65cdba94bc NEWS: Restore the 1.4 release info
I suck...

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:49:32 -08:00
Ben Widawsky
a88cf4cbf1 NEWS: Broadwell will be in 1.6, not 1.5
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:48:17 -08:00
Ben Widawsky
02ee890068 NEWS: Broadwell
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
1c5e1d230b list-workarounds/bdw: Add Broadwell to the list of valid platorms
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-06 09:39:41 -08:00
Mengdong Lin
d566972336 quick_dump/bdw: support Broadwell in device auto-detection
This patch exposes is_broadwell() to python, to be used by device
auto-detection.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Mengdong Lin
ee4318931f quick_dump/bdw: dump audio debug registers for Haswell and Broadwell
A new file "audio_debug_haswell_plus.txt" is created to define audio
debug registers for Haswell and its successors like Broadwell.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Mengdong Lin
0facfb2eb0 quick_dump/bdw: dump audio configuration registers for Haswell and Broadwell
A new file "audio_config_haswell_plus.txt" is created to define audio
configuration registers for Haswell and its successors like Broadwell.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Ben Widawsky
4f1410d978 quick_dump/bdw: Just basic stuff for now
Just the interrupt registers for now.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Mengdong Lin
e35126d30c intel_audio_dump/bdw: dump audio M CTS readback register
This debug register provides test feedback of the audio M values (DP)
or CTS values (HDMI)

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Mengdong Lin
97e5cf6006 intel_audio_dump/bdw: dump audio DP and DIP FIFO debug status
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Mengdong Lin
f075c3c068 intel_audio_dump/bdw: dump audio chicken bit register
This patch dumps this debug register and parse the data for Broadwell.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Mengdong Lin
8535720b4c intel_audio_dump/bdw: dump debug registers for audio immediate commands
This patch dumps debug registers to check audio immediate command, response
and status.

The audio driver will fall back into immediate command mode if normal
communication between controller and codec is dead.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Reviewed-by: Xingchao Wang <xingchao.wang@intel.com>
[Ben: Small printf changes to remove compiler warning]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Mengdong Lin
69cc00b072 intel_audio_dump/bdw: add support for Broadwell
This patch renames Haswell audio dump function and reuses it for Broadwell.

Since Haswell, audio registers are moved from the south display engine to the
north display engine. And the audio register layout is same for Haswell and its
successors like Broadwell.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
c82872b019 rendercopy/bdw: Add AUB annotations for states
This will hopefully help debugging things.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Damien Lespiau
91e5897246 rendercopy/bdw: Fix the original implementation
For posterity, I've squashed these commits against Damien's request.

rendercopy/gen8: Fix the include guards

rendercopy/gen8: Update the 3DSTATE_MULTISAMPLE opcode

The opcode has changed in BDW.

rendercopy/gen8: Add the VF_TOPOLOGY state

The primitive type has moved out of the 3DPRIMITIVE to its own state,
VF_TOPOLOGY.

rendercopy/gen8: Fixup 3STATE_PS

Update the state to the latest BSpec, in particular the thread count was
using a wrong shift and we were missing kernel2 offset.

rendercopy/gen8: Update 3DSTATE_BASE_ADDRESS

This state has seen its fields moved around a bit, follow the BSpec.

rendercopy/gen8: Allocate 64 VUEs

The simulator screams at us if we try to allocate less than that.

rendercopy/gen8: Surface states have to be 64 bytes a aligned

rendercopy/gen8: Vertical/horizontal align 2 does not exist any more

So set them to 4. This should not matter with rendercopy (which is not
using compressed textures), but it makes the simulator moan.

rendercopy/gen8: Make sure the vertex buffer is 8 bytes aligned

rendercopy/gen8: Adjust 3DSTATE_VERTEX_BUFFERS for gen8

The address of the buffer is now on 48 bits. Also the size was computed
as offset + size where the field is really the size of the buffer
itself, not the end address.

rendercopy/gen8: Update the SF/SBE states for gen8

gen8 has a few changes around those states and a new ones RASTER and
SBE_SWIZ.

rendercopy/gen8: Add the PS_EXTRA and PS_BLEND states

rendercopy/gen8: Fix building with DEBUG_RENDERCOPY defined

The forward declaration was missing the final ';'. Let's move the whole
function at the top instead.

rendercopy/gen8: Update the PS and CONSTANT_PS states

rendercopy/gen8: Fix the red channel selection

Make it output red.

rendercopy/gen8: Update the write -1 shader

With the latest assembler changes from Haihao.

rendercopy/gen8: Remove blit.g8a

There is no diff between this file and blig.g7a. Remove it.

rendercopy/gen8: Fix the surface relocation offset

The surface base address is now at dwords 8/9 so the relocation has to
mirror the change.

rendercopy/gen8: Add the VF_INSTANCING state

Should work without, but doesn't hurt to add it.

rendercopy/gen8: Set the Attribule enable field in PS_EXTRA

When the SF is set up to output some attributes, the pixel shader also
have to be told there's attributes to care about.

rendercopy/gen8: Set the force bits to read URB offset/length

If we want to override the URB offset/length in the SBE state itself, we
need to set the force bits on (new in gen8)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
3f0714a860 rendercopy/bdw: Add gen8_render.h to the file list
So it gets distributed with make dist.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Jesse Barnes
3edfff16cd rendercopy/bdw: Initial gen8 rendercopy
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06 09:39:41 -08:00
Zhao Yakui
66783e4c4f assembler/bdw: Add the DATA_PORT_CACHE1 shared function for Gen8+
This is required to send some messages to data port in GPU shader.
For example: media_block_write message.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Zhao Yakui
88e5f1fdf8 assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
60c9b41e11 assembler/bdw: SEND instruction
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Ben Widawsky
3d8d094efe assembler/bdw: Small cleanup
This was originally part of:

commit 62298329350b965e4bbfc558e5a4b1b3646742ea
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date:   Wed Aug 14 14:21:16 2013 -0700

    assembler: error for the wrong syntax of SEND instruction on GEN6+

I merged that patch separately, but this tiny hunk was leftover. In
order to not muck in changing too much history, I am leaving this as a
discrete patch, but with the changed commit message

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
bf05bd5531 assembler/bdw: Check & Refinement Engine message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
b6a33bdcce assembler/bdw: Video Motion Estimation(VME) message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
bf003ea634 assembler/bdw: Thread Spawn message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
01c9654a65 assembler/bdw: Data port message
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
9d0287c252 assembler/bdw: Set thread switch for multiple branch instructions
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
216163b44d assembler/bdw: Set jip/uip offsets used by flow control instructions
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
2df4d3115a assembler/bdw: Disable mask control for advanced mode
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Xiang, Haihao
220f165008 assembler/bdw: Set math function
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
9cf8e1b79c assembler/bdw: Use gen8_set_exec_size() to set the execution size
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:41 -08:00
Damien Lespiau
f9e74fb494 assembler/bdw: Preliminary gen8 send & msgtarget support
Still some work needed there, but enough for rendercopy.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:40 -08:00
Damien Lespiau
bc3bf098a9 assembler/bdw: Add the start of a gen8 disassembler
Directly taken from Mesa.

v2 (Ben): Updated copyright

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:39:28 -08:00
Damien Lespiau
42d8d57c8c assembler/bdw: Make the validation functions take a brw_program_instruction
This allows to use the same functions to validate operands on gen8 for
now.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:36 -08:00
Damien Lespiau
af4d37de38 assembler/bdw: Support some basic gen8 intructions
We should now support alu2 intructions with direct register addressing.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Damien Lespiau
c3b36592af assembler/bdw: Add gen8_instruction from mesa
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
f57f55e4da tests/bdw: Port storedw_loop_vebox to gen8
I chose not to implement this in the same way as Zhao Yakui because I
was lazy.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Zhao Yakui
50a52f3ada tests/bdw: Port storedw_loop_blt to gen8
The code is from the storedw_loop_render.

v2 (by Ben): Flush on the correct ring

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Zhao Yakui
6a2d5059ff tests/bdw: Port storedw_loop_bsd to gen8
The code is from the storedw_loop_render.

v2 (by Ben): Flush on the correct Ring

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Damien Lespiau
636f726b80 tests/bdw: Port storedw_loop_render to bdw
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
3aad2ac83c tests/bdw: pwrite_pread
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
d348022934 tests/bdw: gem_linear_blits
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
adc5a41f2b tests/bdw: gem_pin
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
eb89ce7a7e tests/bdw: gem_exec_blt
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
91f9e19fcd tests/bdw: gem_evict_*
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
6fa529ecd6 tests/bdw: gem_cpu_reloc
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
3e2937bd99 tests/bdw: gem_exec_faulting_reloc
support gen8 style blits

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06 09:34:35 -08:00
Ben Widawsky
f4dfa37e85 bdw: Update obvious missing blit support
This provides a macro that allows us to update all the arbitrary blit
commands we have stuck throughout the code. It assumes we don't actually
use 64b relocs (which is currently true). This also allows us to easily find
all the areas we need to update later when we really use the upper dword.

This block was done mostly with a sed job, and represents the easier
in test blit implementations.

v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
2013-11-06 09:34:35 -08:00