In the future, we may like to enable wc mapping of at least the GATT,
and so causing a conflict if we attempt to map the entire bar as uc-
here. Obviously we need a better fallback plan, but for the moment only
attempt to map the portion of the pci space that we use for register
access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Solaris <sys/types.h> already has #define NOPID (pid_t)(-1)
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With the option '-r', the testdisplay could paint a 2-D bar code(QR
bar code) on the screen. The word "pass" is hiden in the bar code
image. Further more, with this option, testdisplay will wait until a
system signal 'SIGUSR1' coming after each mode setting. This function
is for another program to control testdisplay.
danvet: Fix up the missing static.
Signed-off-by: Yi Sun <yi.sun@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This wraps libdrm functionality to exec with contexts. This patch
shouldn't be applied until libdrm for contexts is updated.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
When looking at the pwrite/pread/wc performance, it is useful to judge
that against the performance of an ordinary CPU mmap.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Using BEGIN_BATCH can lead to a nice inf recursion through require_space
-> flush_batch -> BEGIN_BATCH.
Also fix things up to always require BATCH_RESERVED. We need 2 dwords
for the gen5 workaround and 2 dwords for MI_BB_END.
We should get more kms tests soon, and not needing to copy-paste a
nice test pattern should be useful.
That establishes a firm depency of i-g-t on cairo over everything, but
I don't care so much about that.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For now, only print their content for diffing, but also add the necessary
bits that can be used for more verbose output in the fugure.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Unfortunately this requires slab poisoning to catch anything :(
Also add a new helper to drmtest to get the available fence count.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Although the address space for GTT mappings may only be 32-bits, we need
to use the explicit 64-bit mmap interface so that on a 32-bit platform
the offset we pass is not truncated to 31-bits.
Fixes gem_mmap_offset_exhaustion on 32-bit platforms.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This is meant to test the sysfs entry for showing rc6 residency in
milliseconds. Remember, sysfs is a permanent interface.
v2: use new get_card interface to try "all" devices
check rc6p and rc6pp in addition to rc6
v3: rename rc6_residency.c to sysfs_rc6_residency.c
print better error messages
skip test if rc6 isn't enabled
v4: update to new sysfs names
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Currently all we see is gem_read: ret == 0 failed, where it would help
to see the errno and/or the ret.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
MI_MEM_VIRTUAL actually means use global gtt now, not setting the bit
means use ppgtt. On previous gens, not setting the bits ment 'use
physical memory'. So what, the usual confusion.
Note that for some odd reasong this is broken on gen6, but only on the
bsd ring. Unexpected.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Oops, my mistake for copying a compile fix from another machine...
If we can't detect how much RAM we have, 0 is not a suitable default, so
keep the error for the time being and only downgrade the error for
unknown swap.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
On SandyBridge, the BLT commands were split from the RENDER commands as
well as the BSD split inherited from Ironlake. So we need to make sure
we do exercise each ring, and in order to do so we also need to make
sure each batch takes longer to execute than it takes for us to
submit it.
v2: Exercise each ring sequentially.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
I was interested in finding why my IVB system is not getting GPU turbo
after suspend/resume. The piece that looks weird to me is that
INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's
0x12000000.
On my system, sys/fcntl.h contains exactly one line:
#include <fcntl.h>
So there's really no need to #ifdef it. Also, intel_mmio.c already
included <fcntl.h>; there's no need to include it twice.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Added the Android.mk file as per Android make system. Also had to modify
the headers with the proper location for fcntl.h as per the Android
bionic headers location
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
There may be some updates required, but assuming Ivybridge is similar to
Sandybridge is a decent start; previously it fell through to the Gen2/3
case and nothing worked.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
