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https://github.com/tiagovignatti/intel-gpu-tools.git
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tests: adapt storedw tests to ppgtt
MI_MEM_VIRTUAL actually means use global gtt now, not setting the bit means use ppgtt. On previous gens, not setting the bits ment 'use physical memory'. So what, the usual confusion. Note that for some odd reasong this is broken on gen6, but only on the bsd ring. Unexpected. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -57,6 +57,20 @@ is_intel(int fd)
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return IS_INTEL(devid);
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}
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bool gem_uses_aliasing_ppgtt(int fd)
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{
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struct drm_i915_getparam gp;
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int val;
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gp.param = 18; /* HAS_ALIASING_PPGTT */
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gp.value = &val;
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if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
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return 0;
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return val;
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}
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/* Ensure the gpu is idle by launching a nop execbuf and stalling for it. */
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void gem_quiescent_gpu(int fd)
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{
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@ -30,6 +30,7 @@
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#include <unistd.h>
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include "xf86drm.h"
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#include "intel_batchbuffer.h"
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@ -53,6 +54,9 @@ uint64_t gem_aperture_size(int fd);
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uint64_t gem_mappable_aperture_size(void);
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int gem_madvise(int fd, uint32_t handle, int state);
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/* feature test helpers */
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bool gem_uses_aliasing_ppgtt(int fd);
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/* generally useful helpers */
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void drmtest_fork_signal_helper(void);
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void drmtest_stop_signal_helper(void);
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@ -44,6 +44,7 @@
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static drm_intel_bufmgr *bufmgr;
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static drm_intel_bo *target_bo;
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static int has_ppgtt = 0;
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/* Like the store dword test, but we create new command buffers each time */
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static void
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@ -53,7 +54,9 @@ store_dword_loop(void)
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uint32_t *buf;
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drm_intel_bo *cmd_bo;
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cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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cmd = MI_STORE_DWORD_IMM;
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if (!has_ppgtt)
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cmd |= MI_MEM_VIRTUAL;
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for (i = 0; i < 0x80000; i++) {
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cmd_bo = drm_intel_bo_alloc(bufmgr, "cmd bo", 4096, 4096);
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@ -136,6 +139,8 @@ int main(int argc, char **argv)
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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has_ppgtt = gem_uses_aliasing_ppgtt(fd);
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if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
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fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and"
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@ -45,6 +45,7 @@
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static drm_intel_bo *target_buffer;
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static int has_ppgtt = 0;
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/*
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* Testcase: Basic blitter MI check using MI_STORE_DATA_IMM
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@ -56,7 +57,9 @@ store_dword_loop(void)
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int cmd, i, val = 0;
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uint32_t *buf;
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cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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cmd = MI_STORE_DWORD_IMM;
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if (!has_ppgtt)
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cmd |= MI_MEM_VIRTUAL;
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for (i = 0; i < 0x100000; i++) {
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BEGIN_BATCH(4);
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@ -105,6 +108,8 @@ int main(int argc, char **argv)
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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has_ppgtt = gem_uses_aliasing_ppgtt(fd);
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if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
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fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
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@ -112,8 +117,11 @@ int main(int argc, char **argv)
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return 77;
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}
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/* This supposedly only works with ppgtt */
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return 77;
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/* This only works with ppgtt */
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if (!has_ppgtt) {
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fprintf(stderr, "no ppgtt detected, which is required\n");
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return 77;
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}
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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if (!bufmgr) {
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@ -45,6 +45,7 @@
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static drm_intel_bo *target_buffer;
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static int has_ppgtt = 0;
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/*
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* Testcase: Basic bsd MI check using MI_STORE_DATA_IMM
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@ -56,7 +57,9 @@ store_dword_loop(void)
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int cmd, i, val = 0;
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uint32_t *buf;
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cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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cmd = MI_STORE_DWORD_IMM;
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if (!has_ppgtt)
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cmd |= MI_MEM_VIRTUAL;
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for (i = 0; i < 0x100000; i++) {
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BEGIN_BATCH(4);
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@ -105,6 +108,8 @@ int main(int argc, char **argv)
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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has_ppgtt = gem_uses_aliasing_ppgtt(fd);
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if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
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fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
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@ -112,8 +117,17 @@ int main(int argc, char **argv)
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return 77;
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}
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/* This supposedly only works with ppgtt */
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return 77;
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if (IS_GEN6(devid)) {
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fprintf(stderr, "MI_STORE_DATA broken on gen6 bsd\n");
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return 77;
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}
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/* This only works with ppgtt */
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if (!has_ppgtt) {
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fprintf(stderr, "no ppgtt detected, which is required\n");
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return 77;
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}
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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if (!bufmgr) {
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@ -45,6 +45,7 @@
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static drm_intel_bo *target_buffer;
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static int has_ppgtt = 0;
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/*
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* Testcase: Basic render MI check using MI_STORE_DATA_IMM
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@ -56,7 +57,9 @@ store_dword_loop(void)
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int cmd, i, val = 0;
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uint32_t *buf;
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cmd = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
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cmd = MI_STORE_DWORD_IMM;
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if (!has_ppgtt)
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cmd |= MI_MEM_VIRTUAL;
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for (i = 0; i < 0x100000; i++) {
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BEGIN_BATCH(4);
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@ -105,6 +108,8 @@ int main(int argc, char **argv)
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fd = drm_open_any();
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devid = intel_get_drm_devid(fd);
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has_ppgtt = gem_uses_aliasing_ppgtt(fd);
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if (IS_GEN2(devid) || IS_GEN3(devid) || IS_GEN4(devid) || IS_GEN5(devid)) {
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fprintf(stderr, "MI_STORE_DATA can only use GTT address on gen4+/g33 and "
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