The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Protect the macro argument evaluations with parens.
This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.
v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.
v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This is vital in a multi-GPU system so that we only test the Intel card
and not the discrete GPUs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
