Add the Kabylake GT4 PCI IDs as defined in this kernel patch.
commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d
Author: Deepak S <deepak.s@intel.com>
Date: Wed Oct 28 12:21:12 2015 -0700
drm/i915/kbl: Add Kabylake GT4 PCI ID
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Remove the KBL check from IS_SKYLAKE() following the kernel definition.
Then, add the KBL check to IS_GEN9().
The idea is to avoid confusion. On the kernel side, the mix of SKY
and KBL was nacked so the platforms are split.
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Also, following kernel definition Kabylake is Skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
v2: Rebase on top of the SKL upstreaming
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
In the next patch we'll add support for BXT which is GEN9, but doesn't
have PCH, so fix the macro accordingly.
No functional change.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Only include what the header itself needs. The big fish here is
intel-gpu-tools.h. More will follow.
One ugly thing removed here is the duplicated GEN6_TD_CTL #define, one
of which was broken.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
At DDX commit Chris mentioned the tendency we have of finding out more
PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
When publishing first HSW ids we weren't allowed to use "GT3" codname.
But this is the correct codname and Mesa is using it already.
So to avoid people getting confused why in Mesa it is called GT3 and here
it is called GT2_PLUS let's fix this name in a standard and correct way.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
The second digit was off by one, which meant we accidentally treated
GT(n) as GT(n-1). This also meant no support for GT1 at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Protect the macro argument evaluations with parens.
This is already touching most lines, so while at it, fix up all white
space to uniform style throughout the file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Using a dummy reloc that doesn't matter to trick the kernel into
synchroizing the rings.
v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and
switch to MI_COND_BATCH_BUFFER_END as a dummy command on the
render ring to avoid PIPE_CONTROL errata.
v3: somebody clever decided that in C, you cound from 1,
i.e. I915_EXEC_RENDER == 1. It works now ...
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This is vital in a multi-GPU system so that we only test the Intel card
and not the discrete GPUs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
