v2:
- add a subtest for uncached mappings too for LLC platforms where the
default is cached mapping (Chris)
Signed-off-by: Imre Deak <imre.deak@intel.com>
The integer comparison macros give us better error output by including
the actual values that failed the comparison.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
This reverts commit 3005ac3ee8d7aede73a3e63d2068a6074156ebe5.
QA has done the testing we've wanted.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This reverts commit f00efff326610fdba92dbc91d951790a3320052e.
This is a temporary revert since I want QA to first test with the
original testcase whether it got faster again. This is to test the
effects of
commit 227f782e4667fc622810bce8be8ccdeee45f89c2
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu May 15 10:41:42 2014 +0100
drm/i915: Retire requests before creating a new one
We should revert this revert again as soon as QA has completed
testing.
References: https://bugs.freedesktop.org/show_bug.cgi?id=78024
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
These tests are really for catching TLB or GTT mapping failures due to
bad programming in the kernel driver. We've never needed more than a
few pages worth of data write to actually see those.
All the cases that simply dump some debug information and couldn't be
converted to some of the fancier macros.
Some information output removed when it's redundant with the subtest
status.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
With the header cleanup we can now give this header a suitable name,
since it now really only contains register access and other I/O
functions and assorted definitions.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Only the igt core and non-test tools should have asserts to catch
internal errors, tests and helper libraries should all user igt_asert
instead.
Fix things up where assert instead of igt_assert was used.
One tiny step towards header sanity.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
My git failures are truly remarkable. I ended up pushing the wrong
commit here:
commit 1552aa21124cabe762862bb414490510415a2b2d
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date: Mon Jan 13 06:28:45 2014 -0800
gem_storedw_batches_loop: Fix for BDW
This puts the offset of the reloc in the wrong place for pre-BDW
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73866
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Existing code was trying to be too clever and wasn't properly emitting
the high dword, or the correct length.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
In the past new testcases with subtest often forgot to add the call to
igt_exit at the end of their main() function. That is now caught with
a bit more obnoxious asserts, but it's still a nuissance.
This little igt_main macro takes care of that (and also of calling the
subtest machinery initialization code correctly).
If no one objects I'll roll this out for all the simple cases (i.e.
those tests that don't have additional argv parsing on top of the
subtest machinery).
v2: Roll it out across the board.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ben Widawsky suggested to use vasprintf, which perfectly fits the bill.
Also fix the logic conversion bug in tests/gem_storedw_batches_loop that
crept in again :(
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Mostly a sed job with too manual fixups:
- one case of using _exit instead of exit
- and one case which under some conditions use 77, so convert that
check to an igt_skip.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Requested-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
We tweak the tests marked as runnable in simulation to run more quickly,
more often then not at the expense of stress testing (which is of an
arguable interest for the initial bring up in simulation). Hopefully the
values chosen still test something, which is not always straightforward.
It does run quickly, the number on an IVB machines are:
$ time sudo IGT_SIMULATION=0 ./piglit-run.py tests/igt.tests foo
[...]
real 2m0.141s
user 0m16.365s
sys 1m33.382s
Vs.
$ time sudo IGT_SIMULATION=1 ./piglit-run.py tests/igt.tests foo
[...]
real 0m0.448s
user 0m0.226s
sys 0m0.183s
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Let's start by a small set of tests, to eventually consider running
more.
The current list should then be:
gem_mmap
gem_pread_after_blit
gem_ring_sync_loop
gem_ctx_basic
gem_pipe_control_store_loop
gem_storedw_loop_render
gem_storedw_loop_blt
gem_storedw_loop_bsd
gem_render_linear_blits
gem_tiled_blits
gem_cpu_reloc
gem_exec_nop
gem_mmap_gtt
v2 add (Daniel Vetter)
gem_exec_bad_domains
gem_exec_faulting_reloc
gem_flink
gem_reg_read
gem_reloc_overflow
gem_tiling_max_stride
prime_*
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
MI_MEM_VIRTUAL actually means use global gtt now, not setting the bit
means use ppgtt. On previous gens, not setting the bits ment 'use
physical memory'. So what, the usual confusion.
Note that for some odd reasong this is broken on gen6, but only on the
bsd ring. Unexpected.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
MI_*/PIPE_CONTROL writes need to be in DOMAIN_INSTRUCTION, because
that is what mesa uses and I plan to use this to work around a
gen6 ppgtt issue.
Also testing with intentionally b0rked GFX_MODE on my snb shows that
we need to increase the loop counter a bit to reliably hit the tlb
invalidation problem. Test still completes within a few seconds.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Add a couple of simple store dword tests to test memory coherence.
gem_storedw_loop simply executes a batch that continually stores an
incremented value to a target buffer object, checking the results after
each batch completes.
gem_storedw_batches_loop does the same thing, but creates a new command
batch buffer for each iteration, which can exercise the buffer creation
code. This test is based on one from Andrzej Kacprowski from Intel.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
