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8dc95202c8
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
446 lines
15 KiB
C
446 lines
15 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/** @file gen8_instruction.cpp
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*
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* A representation of a Gen8+ EU instruction, with helper methods to get
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* and set various fields. This is the actual hardware format.
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*/
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#include "brw_defines.h"
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#include "gen8_instruction.h"
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void
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gen8_set_dst(struct gen8_instruction *inst, struct brw_reg reg)
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{
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/* MRFs haven't existed since Gen7, so we better not be using them. */
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if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
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reg.file = BRW_GENERAL_REGISTER_FILE;
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reg.nr += GEN7_MRF_HACK_START;
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}
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assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
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if (reg.file == BRW_GENERAL_REGISTER_FILE)
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assert(reg.nr < BRW_MAX_GRF);
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gen8_set_dst_reg_file(inst, reg.file);
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gen8_set_dst_reg_type(inst, reg.type);
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if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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gen8_set_dst_da_reg_nr(inst, reg.nr);
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if (gen8_access_mode(inst) == BRW_ALIGN_1) {
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/* Set Dst.SubRegNum[4:0] */
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gen8_set_dst_da1_subreg_nr(inst, reg.subnr);
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/* Set Dst.HorzStride */
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if (reg.hstride == BRW_HORIZONTAL_STRIDE_0)
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reg.hstride = BRW_HORIZONTAL_STRIDE_1;
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gen8_set_dst_da1_hstride(inst, reg.hstride);
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} else {
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/* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
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assert(reg.subnr == 0 || reg.subnr == 16);
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gen8_set_dst_da16_subreg_nr(inst, reg.subnr >> 4);
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gen8_set_da16_writemask(inst, reg.dw1.bits.writemask);
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}
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} else {
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/* Indirect mode */
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assert (gen8_access_mode(inst) == BRW_ALIGN_1);
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gen8_set_dst_addr_mode(inst, BRW_ADDRESS_REGISTER_INDIRECT_REGISTER);
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/* Set Dst.HorzStride */
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if (reg.hstride == BRW_HORIZONTAL_STRIDE_0)
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reg.hstride = BRW_HORIZONTAL_STRIDE_1;
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gen8_set_dst_da1_hstride(inst, reg.hstride);
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gen8_set_dst_ida1_sub_nr(inst, reg.subnr);
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gen8_set_dst_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK));
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if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK)
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gen8_set_dst_ida1_imm9(inst, 1);
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else
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gen8_set_dst_ida1_imm9(inst, 0);
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}
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/* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
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* or 16 (SIMD16), as that's normally correct. However, when dealing with
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* small registers, we automatically reduce it to match the register size.
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*/
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if (reg.width < BRW_EXECUTE_8)
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gen8_set_exec_size(inst, reg.width);
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}
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static void
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gen8_validate_reg(struct gen8_instruction *inst, struct brw_reg reg)
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{
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int hstride_for_reg[] = {0, 1, 2, 4};
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int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
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int width_for_reg[] = {1, 2, 4, 8, 16};
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int execsize_for_reg[] = {1, 2, 4, 8, 16};
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int width, hstride, vstride, execsize;
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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/* TODO: check immediate vectors */
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return;
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}
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if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE)
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return;
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assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg));
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hstride = hstride_for_reg[reg.hstride];
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if (reg.vstride == 0xf) {
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vstride = -1;
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} else {
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assert(reg.vstride >= 0 && reg.vstride < Elements(vstride_for_reg));
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vstride = vstride_for_reg[reg.vstride];
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}
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assert(reg.width >= 0 && reg.width < Elements(width_for_reg));
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width = width_for_reg[reg.width];
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assert(gen8_exec_size(inst) >= 0 &&
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gen8_exec_size(inst) < Elements(execsize_for_reg));
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execsize = execsize_for_reg[gen8_exec_size(inst)];
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/* Restrictions from 3.3.10: Register Region Restrictions. */
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/* 3. */
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assert(execsize >= width);
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/* 4. */
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if (execsize == width && hstride != 0) {
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assert(vstride == -1 || vstride == width * hstride);
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}
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/* 5. */
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if (execsize == width && hstride == 0) {
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/* no restriction on vstride. */
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}
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/* 6. */
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if (width == 1) {
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assert(hstride == 0);
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}
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/* 7. */
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if (execsize == 1 && width == 1) {
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assert(hstride == 0);
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assert(vstride == 0);
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}
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/* 8. */
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if (vstride == 0 && hstride == 0) {
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assert(width == 1);
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}
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/* 10. Check destination issues. */
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}
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void
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gen8_set_src0(struct gen8_instruction *inst, struct brw_reg reg)
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{
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/* MRFs haven't existed since Gen7, so we better not be using them. */
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if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
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reg.file = BRW_GENERAL_REGISTER_FILE;
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reg.nr += GEN7_MRF_HACK_START;
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}
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if (reg.file == BRW_GENERAL_REGISTER_FILE)
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assert(reg.nr < BRW_MAX_GRF);
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gen8_validate_reg(inst, reg);
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gen8_set_src0_reg_file(inst, reg.file);
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gen8_set_src0_reg_type(inst, reg.type);
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gen8_set_src0_abs(inst, reg.abs);
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gen8_set_src0_negate(inst, reg.negate);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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inst->data[3] = reg.dw1.ud;
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/* Required to set some fields in src1 as well: */
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gen8_set_src1_reg_file(inst, 0); /* arf */
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gen8_set_src1_reg_type(inst, reg.type);
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} else if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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gen8_set_src0_da_reg_nr(inst, reg.nr);
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if (gen8_access_mode(inst) == BRW_ALIGN_1) {
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/* Set Src0.SubRegNum[4:0] */
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gen8_set_src0_da1_subreg_nr(inst, reg.subnr);
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if (reg.width == BRW_WIDTH_1 &&
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gen8_exec_size(inst) == BRW_EXECUTE_1) {
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gen8_set_src0_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
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gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
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} else {
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gen8_set_src0_da1_hstride(inst, reg.hstride);
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gen8_set_src0_vert_stride(inst, reg.vstride);
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}
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gen8_set_src0_da1_width(inst, reg.width);
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} else {
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/* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
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assert(reg.subnr == 0 || reg.subnr == 16);
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gen8_set_src0_da16_subreg_nr(inst, reg.subnr >> 4);
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gen8_set_src0_da16_swiz_x(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_X));
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gen8_set_src0_da16_swiz_y(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_Y));
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gen8_set_src0_da16_swiz_z(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_Z));
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gen8_set_src0_da16_swiz_w(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_W));
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/* This is an oddity of the fact that we're using the same
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* descriptions for registers in both Align16 and Align1 modes.
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*/
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if (reg.vstride == BRW_VERTICAL_STRIDE_8)
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gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_4);
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else
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gen8_set_src0_vert_stride(inst, reg.vstride);
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}
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} else if (reg.address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER) {
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assert (gen8_access_mode(inst) == BRW_ALIGN_1);
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if (reg.width == BRW_WIDTH_1 &&
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gen8_exec_size(inst) == BRW_EXECUTE_1) {
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gen8_set_src0_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
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gen8_set_src0_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
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} else {
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gen8_set_src0_da1_hstride(inst, reg.hstride);
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gen8_set_src0_vert_stride(inst, reg.vstride);
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}
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gen8_set_src0_da1_width(inst, reg.width);
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gen8_set_src0_ida1_sub_nr(inst, reg.subnr);
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gen8_set_src0_addr_mode(inst, BRW_ADDRESS_REGISTER_INDIRECT_REGISTER);
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gen8_set_src0_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK));
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if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK)
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gen8_set_src0_ida1_imm9(inst, 1);
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else
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gen8_set_src0_ida1_imm9(inst, 0);
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}
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}
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void
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gen8_set_src1(struct gen8_instruction *inst, struct brw_reg reg)
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{
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/* MRFs haven't existed since Gen7, so we better not be using them. */
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if (reg.file == BRW_MESSAGE_REGISTER_FILE) {
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reg.file = BRW_GENERAL_REGISTER_FILE;
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reg.nr += GEN7_MRF_HACK_START;
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}
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if (reg.file == BRW_GENERAL_REGISTER_FILE)
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assert(reg.nr < BRW_MAX_GRF);
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gen8_validate_reg(inst, reg);
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gen8_set_src1_reg_file(inst, reg.file);
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gen8_set_src1_reg_type(inst, reg.type);
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gen8_set_src1_abs(inst, reg.abs);
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gen8_set_src1_negate(inst, reg.negate);
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/* Only src1 can be an immediate in two-argument instructions. */
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assert(gen8_src0_reg_file(inst) != BRW_IMMEDIATE_VALUE);
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if (reg.file == BRW_IMMEDIATE_VALUE) {
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inst->data[3] = reg.dw1.ud;
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} else if (reg.address_mode == BRW_ADDRESS_DIRECT) {
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gen8_set_src1_da_reg_nr(inst, reg.nr);
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if (gen8_access_mode(inst) == BRW_ALIGN_1) {
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/* Set Src0.SubRegNum[4:0] */
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gen8_set_src1_da1_subreg_nr(inst, reg.subnr);
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if (reg.width == BRW_WIDTH_1 &&
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gen8_exec_size(inst) == BRW_EXECUTE_1) {
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gen8_set_src1_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
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gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
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} else {
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gen8_set_src1_da1_hstride(inst, reg.hstride);
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gen8_set_src1_vert_stride(inst, reg.vstride);
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}
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gen8_set_src1_da1_width(inst, reg.width);
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} else {
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/* Align16 SubRegNum only has a single bit (bit 4; bits 3:0 MBZ). */
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assert(reg.subnr == 0 || reg.subnr == 16);
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gen8_set_src1_da16_subreg_nr(inst, reg.subnr >> 4);
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gen8_set_src1_da16_swiz_x(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_X));
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gen8_set_src1_da16_swiz_y(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_Y));
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gen8_set_src1_da16_swiz_z(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_Z));
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gen8_set_src1_da16_swiz_w(inst,
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BRW_GET_SWZ(reg.dw1.bits.swizzle,
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BRW_CHANNEL_W));
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/* This is an oddity of the fact that we're using the same
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* descriptions for registers in both Align16 and Align1 modes.
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*/
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if (reg.vstride == BRW_VERTICAL_STRIDE_8)
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gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_4);
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else
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gen8_set_src1_vert_stride(inst, reg.vstride);
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}
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} else if (reg.address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER) {
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assert (gen8_access_mode(inst) == BRW_ALIGN_1);
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if (reg.width == BRW_WIDTH_1 &&
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gen8_exec_size(inst) == BRW_EXECUTE_1) {
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gen8_set_src1_da1_hstride(inst, BRW_HORIZONTAL_STRIDE_0);
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gen8_set_src1_vert_stride(inst, BRW_VERTICAL_STRIDE_0);
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} else {
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gen8_set_src1_da1_hstride(inst, reg.hstride);
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gen8_set_src1_vert_stride(inst, reg.vstride);
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}
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gen8_set_src1_da1_width(inst, reg.width);
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gen8_set_src1_ida1_sub_nr(inst, reg.subnr);
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gen8_set_src1_addr_mode(inst, BRW_ADDRESS_REGISTER_INDIRECT_REGISTER);
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gen8_set_src1_ida1_imm8(inst, (reg.dw1.bits.indirect_offset & IMM8_MASK));
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if ((reg.dw1.bits.indirect_offset & IMM9_MASK) == IMM9_MASK)
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gen8_set_src1_ida1_imm9(inst, 1);
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else
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gen8_set_src1_ida1_imm9(inst, 0);
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}
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}
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/**
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* Set the Message Descriptor and Extended Message Descriptor fields
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* for SEND messages.
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*
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* \note This zeroes out the Function Control bits, so it must be called
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* \b before filling out any message-specific data. Callers can
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* choose not to fill in irrelevant bits; they will be zero.
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*/
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static void
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gen8_set_message_descriptor(struct gen8_instruction *inst,
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enum brw_message_target sfid,
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unsigned msg_length,
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unsigned response_length,
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bool header_present,
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bool end_of_thread)
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{
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gen8_set_src1(inst, brw_imm_d(0));
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gen8_set_sfid(inst, sfid);
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gen8_set_mlen(inst, msg_length);
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gen8_set_rlen(inst, response_length);
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gen8_set_header_present(inst, header_present);
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gen8_set_eot(inst, end_of_thread);
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}
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void
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gen8_set_urb_message(struct gen8_instruction *inst,
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unsigned opcode,
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unsigned msg_length,
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unsigned response_length,
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bool end_of_thread,
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unsigned offset,
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bool interleave)
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{
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gen8_set_message_descriptor(inst, BRW_SFID_URB, msg_length, response_length,
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true, end_of_thread);
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gen8_set_src0(inst, brw_vec8_grf(GEN7_MRF_HACK_START + 1, 0));
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gen8_set_urb_opcode(inst, 0); /* URB_WRITE_HWORD */
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gen8_set_urb_global_offset(inst, offset);
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gen8_set_urb_interleave(inst, interleave);
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/* per_slot_offset = 0 makes it ignore offsets in message header */
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gen8_set_urb_per_slot_offset(inst, 0);
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}
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void
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gen8_set_sampler_message(struct gen8_instruction *inst,
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unsigned binding_table_index,
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unsigned sampler,
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unsigned msg_type,
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unsigned response_length,
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unsigned msg_length,
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bool header_present,
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unsigned simd_mode)
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{
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gen8_set_message_descriptor(inst, BRW_SFID_SAMPLER, msg_length,
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response_length, header_present, false);
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gen8_set_binding_table_index(inst, binding_table_index);
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gen8_set_sampler(inst, sampler);
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gen8_set_sampler_msg_type(inst, msg_type);
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gen8_set_sampler_simd_mode(inst, simd_mode);
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}
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void
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gen8_set_dp_message(struct gen8_instruction *inst,
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enum brw_message_target sfid,
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unsigned binding_table_index,
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unsigned msg_type,
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unsigned msg_control,
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unsigned mlen,
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unsigned rlen,
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bool header_present,
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bool end_of_thread)
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{
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/* Binding table index is from 0..255 */
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assert((binding_table_index & 0xff) == binding_table_index);
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/* Message Type is only 5 bits */
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assert((msg_type & 0x1f) == msg_type);
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/* Message Control is only 6 bits */
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assert((msg_control & 0x3f) == msg_control);
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gen8_set_message_descriptor(inst, sfid, mlen, rlen, header_present,
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|
end_of_thread);
|
|
gen8_set_function_control(inst,
|
|
binding_table_index | msg_type << 14 | msg_control << 8);
|
|
}
|
|
|
|
|
|
void
|
|
gen9_set_send_extdesc(struct gen8_instruction *inst,
|
|
unsigned int value)
|
|
{
|
|
unsigned int extdesc;
|
|
|
|
extdesc = (value >> 16) & 0x0f;
|
|
gen8_set_bits(inst, 67, 64, extdesc);
|
|
|
|
extdesc = (value >> 20) & 0x0f;
|
|
gen8_set_bits(inst, 83, 80, extdesc);
|
|
|
|
extdesc = (value >> 24) & 0x0f;
|
|
gen8_set_bits(inst, 88, 85, extdesc);
|
|
|
|
extdesc = (value >> 28) & 0x0f;
|
|
gen8_set_bits(inst, 94, 91, extdesc);
|
|
}
|