flywithu/ntel-gpu-tools
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3 Commits

Author SHA1 Message Date
Zhao Yakui
8dc95202c8 assembler/skl: update the extdesc field for SEND instruction 
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate
for the extended message descriptors. And some bits of SEND instruction are defined
as the extdesc field.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
 2014-09-30 12:21:03 +01:00
Zhao Yakui
88e5f1fdf8 assembler/bdw: Add the support of align1 register-indirect addressing mode on Gen8 
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
  >add.sat (16) r[a0.5,0]<1>:uw     r[a0.5,0]<16;16,1>:uw  0x0080:uw
  >add.sat (16) r[a0.5,32]<1>:uw    r[a0.5,32]<16;16,1>:uw 0x0080:uw

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-11-06 09:39:41 -08:00
Damien Lespiau
c3b36592af assembler/bdw: Add gen8_instruction from mesa 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2013-11-06 09:34:35 -08:00